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ADC14155 with differential clock

Mike Adkins
Prodigy 10 points
Other Parts Discussed in Thread: ADC14155

Please advise if the ADC14155 clock inputs are compatible with the LVPECL standard when in differential mode (CLK_SEL/DF = VA). The equivalent circuit on page 4 and the digital characteristics on page 8 of datasheet SNAS350H appear to apply only to single-ended mode and don't say much about differential mode. I have a version of my design running with this part and an LVPECL clock. It appears to work perfectly this way, but I want to make sure I'm not just lucky before proceeding to the next phase.

How about LVDS?

Thanks.

 

  • 0
    TI__Expert 4340 points

    Mike,

    Driving the CLK input of this device with an LVPECL or LVDS signal is not recommended. The datasheet indicates the input receiver to be an inverter device which requires a signal that satisfies the specified VIN(0) and VIN(1). This receiver should not be viewed as having a flexible input common-mode range to accomodate LVPECL and LVDS, but rather a logic input which also accomodates a differential signal that satisfies 3.3V logic levels.

    Regards, Josh