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Better spec alternative to ADS1205 & ADS1204?

Other Parts Discussed in Thread: ADS1204, ADS1205

Hi TI E2E,

I'm getting closer to designing with the ADS1204 or ADS1205 but would like to find a better spec alternative (still 2nd order DS modulator) if possible. Might one of you know if this has become or will become available?

Greetings,

Jesper Mønsted

  • Hi Jesper,

    By better spec alternative, is there anything particular you are looking for?  Are you after better DC performance or AC performance? 

  • Hi Tom, 

    Thanks for asking ;-)

    What I'm mainly looking for is a somewhat higher sampling rate (25 MHz) and better THD/SNR/linearity specs. What would also be most interesting is if TI has a device that is optimized for ultra-low jitter performance preferably so that it accepts an external clock and then internally is optimized to not alter (as is possible) the clock. Could be something like what ESStech do with their ES9018 D/A (very low jitter digital PLL - link here: http://www.esstech.com/PDF/ES9018%20ES9012%20Product%20Brief.pdf).

    BTW I have a few questions on either the ADS1204/1205 which I would appreciate input to either from you or another member here. 

    1. Is either of the ADS1204/ADS1205 likely to work well with a 45.15 MHz clock input? It's specified for a 32 MHz clock but given room for tolerances might it work (well) at 45.15 MHz? I realize it probably will increase heat dissipation but apart from that will it change other parameters significantly?

    2. Is there a optimum way to parallel the outputs from the ADS1204, or can I just do so? What I am considering is a resistor network that allows each of the outputs to be loaded while also providing a sensible output impedance. Yet, if one of you have suggestions for a better way I appreciate hearing about it ....

    Greetings,

    Jesper Mønsted

  • Hi Jesper,

    Great idea!  I'll forward that onto the design team and see what they say, perhaps this is something we can do on the next generation devices.  For paralleling - it would be best to use the external clock and try to equalize the trace lengths to minimize skew.  How many channels do you plan to use?  I don't have any performance curves above the 32 MHz noted in the data sheet, but the various 'typical' curves show that SNR, linearity, gain do start to suffer, so I suspect that would just get worse at 45.15 MHz.

  • Hi Tom,

    Thanks for your input! Would be very interesting to hear if the TI development team would consider making a device that is optimized with respect to the parameters I mention. Not least if they can make it superb in terms of jitter immunity.

    The Esstech device I mention (ES9018) seems to be the de facto standard for highest-end audio D/A converters in the audio community - not least due to its apparently superb jitter reduction DPLL. I realize, though, that jitter issues might be more challenging with a D/A converter since it often gets its clock from a remote device (slave operation) whereas with an A/D converter the clock can be very close to the device itself. However, in an "improved" ADS1204/ADS1205 I guess there there may be ways of optimizing the chip materials & circuitry to obtain really low jitter figures - which would be very interesting to me.

    About parallelling the ADS1204 or 1205, when reading your reply I wonder if I might have been a bit imprecise in asking my question - so just to make sure: What I'd like to do is to e.g. parallel all the inputs & outputs from the ADS1204 so that I sort of "average" the output from the individual channels. Can I do this the way you suggest or would it be more feasible to make a resistor network to connect the individual outputs (channels A to D outputs)? I'm considering "averaging" the four 1 bit digital outputs.

    Greetings,

    Jesper

  • Hi Jesper,

    What is your application here?  Paralleling the inputs should not be a big deal, for the outputs though; are you dealing with the modulator bit-streams digitally or are you passing them through an integrator?

  • Hi Tom,

    Thanks again for replying ... My application is to just record and pass on the 1 bit data most likely via an FPGA. However, I've since decided to not use two of the channels on the ADS1204 - I don't think it'll make much of of a difference - so won't be paralleling them in this round.

    This, on the other hand means that I should decide what to do with the two remaining channels - would you suggest grounding the unused inputs and maybe connect the output to ground via a 50 ohm resistor?

    Greetings from Denmark,

    Jesper Mønsted