spikes in ads62c17 output data

Donald WU

Other Parts Discussed in Thread: ADS62C17

HI, I'm doing a work which uses ads62c17 to acquiste data and send the data to Xilinx FPGA evm ML605. The sampling clock is 100MHZ. we program the adc to output a ramp data to verify the signal integration and find there are some spikes on the ramp, please see the attached picture. We trying lowing the sampling frequency to 50MHZ, but the spikes still there. Also we were trying to adjust the register 44 to shift the CLKOUT egdes but it seemed don't work. could anyone help me?

over 10 years ago

0 Matt Guibord over 10 years ago

TI__Genius 17290 points

Hi Donald,

This does look like a timing issue. Can you provide a block diagram of your FPGA configuration? I'm assuming this is on your own board, not using our EVMs?

Are you using CMOS or LVDS outputs? Did you try all options (including shifting both rising and falling edges) of register 44?

Are both channels showing this problem?

Regards,
Matt Guibord

0 Donald WU over 10 years ago in reply to Matt Guibord

Prodigy 160 points

Hi, Matt;

No, we didn't use TI EVM, but ourselves.

We resolved the trouble, actually, this is because we didn't turn on the lvds ternimation 100 ohm resistors, so it resulted the signal integrity problem. We corrected the FPGA UCF, those spikes disappeared. OMG, we are so naive!

still, thank you a lot!

Donald

0 Matt Guibord over 10 years ago in reply to Donald WU

TI__Genius 17290 points

Hi Donald,

Okay, great! Glad you got it worked out.

Regards,
Matt Guibord

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spikes in ads62c17 output data