Problem of DAC3152 output clock?

OuyangZhao ouyang

Other Parts Discussed in Thread: DAC3152, CDCP1803

Hi,

Now i connect the DAC3152 to TSW1400,There is a clock generate by CDCP1803,and it used as FPGA_CLK that send to TSW1400,For example if the DAC3152 input

clock is 20MHZ,the output of FPGA_CLK is5 MHZ,but i don't know why it is divided by four,what is the function of this clock that send to TSW1400,can we change the number by changing the configuration of CDCP18003.

Thanks,very much.

ouyangZhao,Ouyang

over 11 years ago

0 jim s over 11 years ago

TI__Guru* 91947 points

Ouyang,

The TSW1400 output data is LVDS serdes that requires a clock that is four times slower than the DAC clock. Why do you want to change the CDCP18003 configuration?

Regards,

Jim

0 OuyangZhao ouyang over 11 years ago in reply to jim s

Intellectual 620 points

Hi,

Thanks for you replay,i know the CDCP1803 can realize the output clock divide by 4 or 6 ,8compared with the input clock, i just want to know the FPGA_CLK will have an effect on the TSW1400 ,so we need the clock divide by four that the TSW1400 and DAC3152 can connect and work properly,and we cannot change it ,is that right?

Regards.

Ouyang.

0 Matt Guibord over 11 years ago in reply to OuyangZhao ouyang

TI__Genius 17320 points

Ouyang,

No, you cannot change the clock divider and have the TSW1400 work. The firmware requires a clock 1/4 of the data rate.

Regards,
Matt Guibord

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Problem of DAC3152 output clock?