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Problem of DAC3152 output clock?

Other Parts Discussed in Thread: DAC3152, CDCP1803


    Now i connect the DAC3152 to TSW1400,There is a clock generate by CDCP1803,and it used as FPGA_CLK that send to TSW1400,For example if the DAC3152 input 

clock is 20MHZ,the output of FPGA_CLK is5 MHZ,but i don't know why it is divided by four,what is the function of this clock that send to TSW1400,can we change the number by changing the configuration of CDCP18003.

   Thanks,very much.