Hi All,
We have 4 ADC083000 on our board, and the CLK(1.5GHz) for each ADC083000 is from the same PLL (LMX2531LQ1500)(the layout is well-designed, such that the delay from the PLL to all 4 ADCs are very close). And their DCLK_RST is from the FPGA(XC4VSX35). I have some questions about the synchronization between the 4 ADCs
1) the datasheet says that we can synchronize the ADC through the DCLK_RST pin. There are some timing requirement between the DCLK_RST and the CLK(1.5GHz). However, the CLK(1.5GHz) is from the PLL, while the DCLK_RST is from the FPGA (which doesn't have access to the CLK(1.5GHz)). In this case, does it mean we can't use the DCLK_RST to synchronize the ADC?
2) If we configure all the ADCs first, then turn on the PLL. Will the output of 4 ADCs be synchronized?(As I think all 4 ADC will receive the CLK(1.5GHz) at same time)
We do appreciate if anyone could give us any example/reference about the ADCs synchronization. Thanks a lot!
Thanks
Ben