ADS6145 data accuracy

Hi,

Are you evaluating ADS6145EVM or your proto board?

I suggest you to try the internal test pattern of ADS6145 such as ramp from the register 0x0A. Please refer to the page 18 from the ADS6145 datasheet regarding how to set this register. This is a good start to narrow down the issues. At the same time, are you able to provide the single tone to the input of ADS6145? 10 or 20MHz of input is enough to verify the basic functionality of the general ADC.

Thanks,

KW

KW

In test mode, I tried all zeros, all ones, and toggle.  The output doesn't come out with those spark.  

Does you have any clued where could cause those spark?

Thanks

Zaidi

Hi, Zaidi

Where is your sampling clock source coming from? Is this correlated with analog input frequency? Are you using ADS6145EVM or your own proto board?

Thanks,

KW

Hi, KW

Yes, I am using ADS6145 EVM.

My clock is from one of my ISL5239 board.  Here is my clock screen shot. 125MHz, 2 V p-p.   

thanks

Zaidi

Here is more detail about the clock.  period = 7.99ns.  rise time =  .899ns, fall time = .572ns

Hi, Zaidi

With internal test pattern from ADS6145, there is no spark issue and captured digital output samples are expected, correct?

The captured signal in time domain shows the data format is offset binary, not two's complement. Can you please confirm this?

ADS6145EVM has only LVDS interface but you are testing with CMOS. I guess you did wiring from ADS6145 device pin out to your CMOS type capture card. Is this correct?

Can you please try 10MHz of single tone as analog input of ADS6145EVM and see what will happen in time domain?

Thanks,

KW

Hi KW,

With internal test, there is no spike issue.

The captured signal in time domain are both set two's complement in ADC and my data capture board.  If they are not matching in 2's complement or offset binary, the result will be totally mess up.

ADS6145EVM is controlled through USB cable.  I use all default setting, 2's complement and CMOS mode.  When I order ADS6145 EVM it come with a Samtec to header pin connector 'ADS 614x breakout board'.  The only wiring work I have done is connect the 14 bits to my 18bits capture board which is from MSB(bit 17) to bit 4, and bits 0~3 are not connected.

Here is the sample from 10 MHz single tone analog input.

Thank you 

Zaidi

Have you tried different clock source from signal generator, not from ISL5239 board? The amplitude of clock source would be good enough as 13dBm from signal generator and also I suggest you to synchronize two signal generators, where one is clock source and another is analog input signal.

Thanks,

KW

Hi KW,

You are right there are some clock synchronization problem.  I did internal ramp test again. The below figure is the result.

How can I use  clock at data out J10 pin 2?  I don't see datasheet tell how to use it.   

Thanks!

Zaidi

Hi, Zaidi

With internal ramp pattern, you still have spikes from sampled digital outputs. In general, captured pattern sample should be clean as the previous slide I sent you. As you are using device internal pattern, it's not an issue of analog input signal. If your sampling clock source is good, the only suspicion would be how you capture CMOS output out of LVDS format ADS6145EVM.

J10 of ADS6145EVM is a LVDS connector which is interfaced capture card such as TSW1400. You can order TSW1400 to capture the digital output of ADS6145EVM through online. Please refer to the web sites below. Regarding J10, you can find the schematic also from the user guide of ADS6145EVM web.

ADS6146EVM: http://www.ti.com/tool/ads6145evm

TSW1400: http://www.ti.com/tool/tsw1400evm

Thanks,

KW

Hello, KH

I'm not sure the problem is from clock source or other connection.  I test the ADC output by using USBEE Test Pod.  Both USBEE and ADS6145 wired to same clock, and Here is the sine wave and internal test result. 

Thanks

Zaidi

Hi, Zaidi

Have you tried different values of register 0x0F other than default? The register is for "CMOS output buffer drive strength control". You can try this from GUI, TI ADC SPI Interface. If not working with this, are you able to add external load capacitance around 10pF between ADS6145EVM and your capture board?

Thanks,

KW

Thank you KW, you helped me from I don't know anything about ADC to I know something about ADC.  I think my problem is the ADS 6145 at 125MHz clock rate couldn't well captured 70 MHz signal, because ADS 6145 only captures around 3 samples every 2 period cycles. Some spikes appeared in lower frequency signal.  They are bit errors,  I consider it's acceptable and I can use matlab to apply a  lowpass filter to moveout error bits.

I really appreciated your help and patient.  ^_^

Zaidi Zhu