LVDS Interface between ADS4125EVM and TSW1200EVM

Hi,

You are correct.  Our EVMs are often laid out so that the LVDS can route straight to the connector withou vias, and if there is an inversion then we deal with it in the FPGA firmware.  In general, the data might be inverted in the routing, or the clock, or both.  But the data bits will all be inverted or all not inverted - there won't be some inverted and some not inverted. 

Regards,

Richard P.

Hi,

As per schematic, I guess both clock and data are swapped at connector. With this reverse voltage will be generated at FPGA pin and +ve edge will be -ve edge and vice-versa.

This swapping on clock and data at LVDS connector is making confusion while handling a data inside FPGA.

Please let me know the correct way to latch the design, if you have some VHDL reference design along with pin location details please forward me at

prashant@medhaindia.com

Presently what I am doing inside FPGA is..

.. With LVDS input buffers, clock and data converted to internal signal (VHDL)

..  Derived clock given to IDDR component of FPGA and Dn, Dn+1 latched (Now we have Dn on +ve edge of clock)

.. Inverting each bit given by IDDR o/p.

That's the final data coming from ADC.

Please let me know, whether my design is correct or something I am missing.

Prashant

Hi Prashant,

This sounds correct. Just to clarify, when you say Dn you should be referring to the even bits (D0,D2,D4, etc) and Dn+1 should refer to the odd bits (D1,D3,D5, etc). So you capture the even bits on the rising edge (since clock is inverted) and you capture the odd bits on the falling edge. You then must interleave the even and odd bits to form a full sample.

Regards,
Matt Guibord 

Hi Matt,

Thanks for reply !!

Yes !!!

Dn means even bits (D0,D2,D4, etc) and Dn+1 means odd bits (D1,D3,D5, etc).

Since clock is inverted, at the end of -ve clock, I am rearranging the bits in D11,D10,....,D1,D0.

Then taking the complement of this (as data also inverted) and processing this inverted data as this the correct data.

Which is correct a sample value? Inverted one or true one ??

Can I get a reference design for TSW1200?

Prashant

Prashant,

If the data bits are inverted through the traces as you've indicated, then the correct sample will be the inverse of the capture bits.

Regards,
Matt Guibord 

Hi Matt & Richard,

Coming back to this post, as I am facing some issues for latching ADC data in FPGA.

As I mentioned earlier, Presently what I am doing inside FPGA is..

• With LVDS input buffers, clock and data converted to internal signal (VHDL)
• Derived clock given to IDDR component of FPGA and Dn(even), Dn+1(odd) latched (Now we have Dn on +ve edge of clock)
• Inverting each bit given by IDDR o/p. (Inverting a complete data)

That's the final data coming from ADC.

Questions:

• I am not enabling a LVDS termination for both clk and data of ADC. Do I need to enable it ?
• Do I need to insert some delay through dedicated delay component available in Xilinx FPGAs (like IDELAY)?

Please send me a reference design (RTL code, Pin location file and constraint (.ucf) files) which we have at prashant@medhaindia.com

Thanks And Regards

Prashant

Hi Prashant,

Yes, you absolutely should enable 100 ohm termination for both CLK and data. The LVDS standard requires a 100 ohm termination at the receiving device. We have seen poor results (timing problems, bit errors) when not using termination.

You'll need to analyze the timing of your system, including inserting timing constraints into your FPGA project. Once you insert the correct timing constraints, the Xilinx tool should be able to analyze the timing of your FPGA and indicate any problems. At that point, you can use the IDELAY block to shift the timing (of the clock, or inidividual data bits) to account for any marginal timing. You'll need to consult the Xilinx documentation on how to enter timing constraints. On the ADC side, you'll need to know the setup and hold times which are listed in the datasheet.

Regards,
Matt Guibord