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Data acquisition in the 500MHz range for decay time measurements

flix
Prodigy 40 points
Other Parts Discussed in Thread: ADS5474, LMK02002, CDCE62005, ADS54RF63

Hi,

I would like to use the ADS5474 14bit/400MHz AD, possibly interleaced, to trace a decay curve.

The decay curve will start at a voltage, and then decay typically exponentially to zero.

I just ordered the ADS5474 ADX evaluation board - after reading the documentation I think I will be happy with this.

Just this evaluation board needs a very precise clock from an external 50Ohm source. For my application, it would be best if the sampling clock source could be tuned digitially to values in the range 16 ... 800 MHz ( as I understand this evaluation board wants to sample with minimum 16 MHz, but this is ok for me).

I looked for tunable high precision PLL sources, and came to the LMK02002. Could any specialst tell me, whether this is a good choice, whether this is necessary (or should I just use the FPGA to create the clock)?

Further, on this evaluation board the clock enters the PCB via a transformer (to create a differential signal which is then used inversly for the two ADs). As I understand the LMK02002 datasheet, it has 4 clock outputs which are tunable separately 50...800MHz, and also the delay of each output can be programmed in 8 steps from 0 ... 1.2nsec.

Do you think, it is possible to drive this transformer circuit with the LMK02002 (if possible you perhaps could give me a hit how to drive the transformer), or should I better just use 2 clock outputs of the LMK02002 and connect them directly to the AD clock inputs?

Any further hints or warnings concerning this design will be greatly appreciated!

  • 0
    TI__Intellectual 1255 points

    Clocking from the FPGA is definitely NOT recommended - typical jitter on the FPGA clock can be 50 - 100ps, which can significantly degrade the SNR of the data converters.

    See for example any of the app notes at the end of the message on the effects of jitter on ADC SNR.

     The 0.2ps jitter from the LMK02002 is more in line with what is typically used for high speed data converters, but this would require an external VCXO, which will limit the range of frequencies you can produce. Also, it can be challenging to get the exact VCXO frequency needed with a short lead time.

    My recommendation is to consider the CDCE62005 from TI. This is a PLL with integrated VCO that has good jitter (~ 1ps) and can programmably produce output frequencies across your entire range of 16-800MHz.

    There is an evaluation module available (http://focus.ti.com/docs/toolsw/folders/print/cdce62005evm.html) as well. However, the output is differential, which would need to be convertered to single ended to connect to the ADS5474ADX board.

    http://focus.ti.com/lit/an/slyt338/slyt338.pdf

     

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  • 0 in reply to Robert Murano
    Prodigy 40 points

    Hi Robert, thank you very much for your fast and professional answer. Thank you for the hint with the CDCE62005 and its evaluation board - I just ordered it.

    Please allow one further starter question: On the ADS5474 ADX eval. board, the clock frequency is fed to the two ADs inverted, so that they sample exactly with 180° phase difference.

    In my application (acquisition of a delay line with delay times in the range 10ns-1ms  (of course my system will be the better, the smaller decay times I can measure)) I think the jitter will not be that much critical (as I do not try to calculate a sin wave from 3 or 4 measured points per period, but the decay curve has compared to a sin wave a much lower "analog frequency bandwidth" (I am not a HF expert - please excuse if I use some stupid explanations)).

    The datasheet of the CDCE62005 is quite complex. Before going through it in detail, I just would like to ask for your recommendation: Do you think for the end design, it is necessary to keep the "clock inversion" scheme like in the ADS5474 ADX, or is it possible with the CDCE62005 to use two clock output channels and program the CDCE62005 such, that the phase delay between the tow clock output channels is excactly 180°. If this works, would it be possible to extend this method also to 3 or 4 output channels with 120° or 90° phase delay each? (Then I hope I could relatively easily extend the AD interleaving to 3 or 4 ADs).

    (Or could you give me a hint how to principally best extend the AD interleaving to 3 or 4 ADs?)

    But even if the CDCE62005 could be programmed only for 180° phase inversion, I think it is much easier/smarter to use 2 differential clock outputs of the CDCE62005 and lead them directly to the differential clock inputs of  the two ADs, than to convert the CDCE62005 to single ended and then back to differential.

    PS: I just looked in the CDCE62005 datasheet, and there I saw that there is a possibility to do a "digital phase adjust" - see "Table 23 Output coarse phase adjust settings". There it seems to be possible to adjust the phase to 0 and 180°, and also to 0, 120°, 240°, and also to 0, 90°, 180°, 270°. So if I program the first output to 0°, the 2nd to 90° ... would it be then possible to interleave 4 ADS5474 and thus increase the sampling frequency of the complete system to 1.6GHz?

  • 0 in reply to flix
    TI__Intellectual 1255 points

    For 2 way interleaving, I think using a single output and routing the signal inverted to one ADC will be more accurate. However, it is not clear how your time domain application would be affected by an offset in time of the sample points.

    We actually just released a board with 4x interleaving - the ADS54RF63-adx4

    http://focus.ti.com/docs/toolsw/folders/print/ads54rf63-adx4.html

    This uses fixed delay lines for the 4 ADC clocks. This is probably the most accurate way to do it, but comes at the expense of only being accurate for a single frequency.

    So the key question is in your system, what is the impact of a time offset from interleaving? I wasn't able to find a spec in the CDCE62005 for the skew in phase from ideal between outputs when using the phase shift, but I would guess it would be on the order of 50-100ps. If you can live with this in your application, than this would probably be the easiest and most flexible way to do 4x interleaving.

    Robert

  • 0 in reply to Robert Murano
    Prodigy 40 points

    Thanks for this further very interesting information.

    Unfortunately fixed delay lines will be a bit too inflexible for us - at least if I know that with the CDCE62005 I could get a similar setup with complete flexibility.

    Concerning CDCE62005 I have one important objection, which somehow is not handled in the data sheet: The datasheet defines the power of 1.8-2W for the case of 5 output frequencies 30-490MHz. As for my application with 4 interleaved ADS5474, I would need to run 4 ouputs with 400MHz for full speed operation, I am frightened, the power will increas at least a factor 2-4, if not more, and this definitely I think is a bit much for a QFN housing. I usually would have problems already with the 0.75W which are specvied for the state "Deviders disabled - Outputs disabled" - But I have to admit, that I do not have experience yet with QFN, and as they specify max 29K/W Junction-ambient - it should work with 0.75W.

    Just I looked several times through the complete datasheet, they nowhere specify the time required from the stage "Deviders disabled - Outputs disabled" to the normal operation. I only see, that after sleep, the do a calibration cycle (whose time again is not specifed) - I really would be curious concerning these times. In my application, I typically will measure every 1ms for a time interval of 100usec. So if the startup time from "Deviders disabled - Outputs disabled" to normal operation is in the range of <10usec (as for the ADS5474), then I can live with it nicely. But if this time is larger (e. g. in the msec range as for the 12bit 1GHz ADS54RF63), then I am frightened I need another solution.

    Principally I could also use one CDCE62005 for each ADS5474. Do you think this would work for interleaving - is the delay between input clock and output signal very reproducible in the psec range for this CDCE62005, or is this impossible?

  • 0 in reply to flix
    TI__Mastermind 18095 points

    The CDCE62005 power consumption could be a concern.  When operating with all channels good thermal layout design is required to dissipate the heat from the package.  The CDCE62005 EVM is capable of operating under these conditions without over-dissipating the package.

    I anticipate using a separate CDCE62005 for each device is possible with consitent delays given symmetry with the layout and cable lengths.  If you have further questions related to the details of the CDCE62005 device I encourage you to post your questions to the clocking group forum where our experts will be able to provide more detailed information.