THS5671A: single-ended unipolar I-V output?

(following up to my own question)

Upon careful analysis, it appears that the paragraph in the data sheet refers to two or three variations of the circuit shown in figure 33(b), and there may be a typo as well.

If anyone has a suggestion for how to get 0V to 5V out of the THS5671 without using a -5V supply, then I would appreciate hearing about it.

I'm finding more discrepancies on page 19 of the spec sheet. The second paragraph under "analog current outputs" mentions the compliance range and then goes on to discuss the optimum distortion performance.  Here's where I'm confused again.  It says that the voltage should not exceed 0.5 V, but then suggests a 50 Ω resistor (which is also used in the evaluation board schematic).  A 50 Ω resistor would produce 1.0 V at the maximum output current of 20 mA.  It seems like the IOUT pins should be terminated by a pair of 25 Ω resistors instead, possibly hinted by figure 34(a).

The worst part is the final sentence: "Applications requiring the THS5671A output (i.e., OUT1 and/or OUT2) to extend its output compliance should size RLOAD accordingly."  For one thing, there is no OUT1 or OUT2 output, they're IOUT1 and IOUT2.  More importantly, I would think that you cannot extend the output compliance because I assume it depends upon the internal circuitry of the chip and has a fixed limit.  Does the phrase "extend its output compliance" really mean "maximize the available output compliance?"

I would also like to confirm that the termination resistors are always grounded. The schematic in figure 33(a) and figure 34 seems to imply that the termination is tied to a positive supply like AVDD (because the arrows point up) rather than ground, but I assume current would not flow because the internal switches are fed from AVDD. Figure 32 does show the expected grounding of both termination resistors.

Sorry for all of the questions, but it seems like the spec sheet is self-conflicting. It would be great if someone could review the text, correct any typos, and perhaps revise the spec sheet or issue some kind of change document.

Brian,

let me address some of your questions about the datasheet text.

Q1) Page 19 of the data sheet has a somewhat vague mention of how to obtain single-ended unipolar output from the DAC, assuming it's still operating in I-V configuration.  I would like to use this, so can someone explain what the final sentence "Node IOUT1 should be selected if a single-ended unipolar output is desirable."  The earlier part of the paragraph explains that the op-amp will keep IOUT1 at virtual ground, so I don't understand how the circuit can continue to operate as an I-V converter.  Perhaps I misunderstand what it means to "select" node IOUT1.  Perhaps this is a typo?

A1) The output node IOUT1 will be forced by the opamp feedback to be zero volts to match the + GND input. So when the DAC IOUT1 is fullscale (20 mA), the op amp voltage will be 2V so that 20 mA is generated through the 100 Ohm feedback resistor to cancel the DAC IOUT1 current. When the DAC output is midscale (10mA), the op amp voltage is 1V to generate 10 mA of current. When the DAC output is 0mA, the op amp voltage is 0V since no current is needed. So the transfer function is 1V/10mA.

Q2) Upon careful analysis, it appears that the paragraph in the data sheet refers to two or three variations of the circuit shown in figure 33(b), and there may be a typo as well.

A2) The 3rd configuration is simply when the feedback capacitor Cfb is used to limit the bandwidth. This filtering will cause overshoot, which will swing the output below GND, so a negative voltage is needed to support that configuration.

Q3) I'm finding more discrepancies on page 19 of the spec sheet. The second paragraph under "analog current outputs" mentions the compliance range and then goes on to discuss the optimum distortion performance.  Here's where I'm confused again.  It says that the voltage should not exceed 0.5 V, but then suggests a 50 Ω resistor (which is also used in the evaluation board schematic).  A 50 Ω resistor would produce 1.0 V at the maximum output current of 20 mA.  It seems like the IOUT pins should be terminated by a pair of 25 Ω resistors instead, possibly hinted by figure 34(a).

A3) the configuration in Figure 34 is DOUBLY terminated with 50 Ohms - one at the DAC output and a second as the load. This means the impedance as seen by the DAC output is 50 Ohms in parallel with 50 Ohms, or 25 Ohm. With 25 Ohms, the maximum voltage is 0.5V. You can exceed 0.5V at the DAC output up to 1.25V at the expense of increased distortion.

Q4) The worst part is the final sentence: "Applications requiring the THS5671A output (i.e., OUT1 and/or OUT2) to extend its output compliance should size RLOAD accordingly."  For one thing, there is no OUT1 or OUT2 output, they're IOUT1 and IOUT2.  More importantly, I would think that you cannot extend the output compliance because I assume it depends upon the internal circuitry of the chip and has a fixed limit.  Does the phrase "extend its output compliance" really mean "maximize the available output compliance?"

A4) We will fix the out1 and out2 typos. The sentence "Applications requiring the THS5671A output (i.e., OUT1 and/or OUT2) to extend its output compliance should size RLOAD accordingly." means that to have a voltage swing larger than 0.5V will require a higher impedance load than the 25 Ohms discussed in answer A3 above. For 1V the total impedance needs to be 50 Ohms, for 1.25V it will need to be 62.5 Ohms.

Regarding your system question:

If anyone has a suggestion for how to get 0V to 5V out of the THS5671 without using a -5V supply, then I would appreciate hearing about it.

this sounds like you will need a rail to rail input - rail to rail output op amp. I am going to ask one of my high speed amplifier colleagues to address your question, but if you can send any more requirements like signal BW, etc. I am sure that would help them.

Thank you.  I have a few followup comments.

1) The DAC sources current because it is fed by AVDD. This cause a voltage drop across the 100 Ohm feedback resistor, such that the op-amp voltage will be -2V when the full scale current of 20 mA is flowing.  Likewise, a mid-scale DAC output of 10 mA will produce -1V at the op-amp output. The transfer function should be -1V/10mA. This is consistent with the requirement to use the inverting input, and reflects the basic op-amp current-to-voltage circuit.

The only way to produce a positive voltage would be to insert a current mirror between the DAC and the op-amp, but it would be rather difficult to keep the current mirror at a positive voltage with the op-amp at virtual ground.

4) For clarity, the text should say "extend the output voltage swing" rather than "extend the output compliance range," since the latter cannot be changed beyond the -1V to +1.25V limits.

As for the bandwidth I need, I will be operating the DAC at 2 MSPS or 4 MSPS. The op-amp will be feeding a multiplexed sample-and-hold circuit, so high slew rate would be a good feature.

P.S. Upon reviewing the evaluation board schematic in SLAU032B, I believe that I found a typo on page 3-10 in section 3.6.3 - is there a process for reporting such issues with these documents? I believe that W9 should be connected for the THS3001 to operate as a differential amplifier.

Brian,

I've asked my colleague to look at the thread and he would be better able to answer the specifics of the op amp configuration. However, I think the diagram in the datasheet is a gross simplfication that does not take into account termination resistors and such.

Regarding:

P.S. Upon reviewing the evaluation board schematic in SLAU032B, I believe that I found a typo on page 3-10 in section 3.6.3 - is there a process for reporting such issues with these documents? I believe that W9 should be connected for the THS3001 to operate as a differential amplifier.

Our newer datasheets and User guides contain a link at the bottom of all pages except page 1 called "Submit Document Feedback". If you click on this you will be able to submit feedback that will end up coming to our applications group for review. Older documents do not have this link, but it can be applied for any document using the lit #:

http://www.go-dsp.com/forms/techdoc/doc_feedback.htm?litnum=slau032b

regarding your specific question, inserting W9 grounds the positive op amp input, which will make the output inverted since the negative input is tied to IOUT2. If you have W9 unconnected and W8 installed, both IOUT1 and IOUT2 are used as a differential signal for the op amp inputs.

so I think the document is correct.

Robert

While I am waiting, I should mention that my present design uses the THS4211 instead of the THS3001, THS4001 or THS4011. So far, the THS4211 seems to compare well in terms of cost and capabilities, but I am open to suggestions if changes to the circuit would perform better with another op-amp.

Regarding SLAU032B and its schematic for the THS56X1EVM, W9 does not completely ground the positive op-amp input because there is a 750Ω resistor (R27) in series. The two 750Ω resistors, R27 and R30, act as a voltage divider so that IOUT1 and IOUT2 each have matching gain in the differential circuit. This is basically right out of the textbook on differential op-amp design, which is why I suspect W9 should be connected.

Otherwise, if W9 is open, no current will flow through R30 because no current flows into an op-amp input under steady-state conditions. This might still allow differential operation, but one input will have a different scaling factor than the other, so it will not be truly differential, and the optimum nonlinearity performance will not be achieved.

Sorry if this seems to be getting off-topic, but the THS56X1EVM schematic is important study material for designing a THS5671A output circuit.

Brian,

here is the response from our HS Amp group. Note that the attachment contains a file for use with TI's TINA-TI spice simulator (free download at http://focus.ti.com/docs/toolsw/folders/print/tina-ti.html). I also inlcuded a bitmap of the circuit.

If you have follow up questions, I think we should move this discussion over to the HSAMP forum for better response.

Robert

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First a few comments:

The transimpedance (TIA) design is nice for the DAC since it clamps the DAC output voltage, but it is bad for the amp because it leads to low RF values which will load the output; as in this case, assuming 1 op amp stage, RF needs to be 250 ohm to get 5Vpp out with DAC FS = 20mA. But the design does not lend itself to single supply application; I can make the amp happy if I make the positive input 2.5V (with 5V supply), but that pulls the DAC voltage out of compliance. So this led me to the following solution with 2 amps.

For a 2 op amp solution: (see attached Tina file)

1.     Ideally if we are able to swing from ground to 5V, the design is pretty straight forward:

a)     Use the first amp in TIA with a voltage within the compliance range of the DAC like 1V on positive input. The op amp will clamp the DAC output voltage to 1V. If we make the DAC output current 2mA FS and the TIA gain (set by the feedback resistor) 500, the output of the first amp will swing from 0.0V to 1V (centered around 0.5V).

b)    Then you put the following amp in gain of 5 and its output swings 0V to 5V (centered around 2.5V).

2.     The 1^st problem is the op amp cannot swing this range so you have to tweak things: I based the following on the OPA2830

a)     To keep the output voltages within 0.12V to 4.88V limits of the OPA2830, the voltage on the positive input of the TIA amp needs to be lower and the gains changed which introduces an offset in the final stage.

b)    I used a resistor divider from 5V (supply to ground) to set the voltage on positive input of the TIA amp. I chose the values to give about 10k to ground, which is good for power, but for better offset voltage performance the parallel sum of these 2 resistors should equal the value of the feedback resistor (i.e. about 5X lower). The cap to ground is for noise bypass.

c)     I solved the offset by summing in an inverting gain from the 5V supply with a resistor.

3.     The other issue that need to be address is THS5671A output capacitance = 5pF, which will might make the TIA amp oscillate. So for stability, you need to add 5pF across the feedback resistor of TIA.

For op amp recommendations: this needs negative rail input (or RR input will work too) and as close to RR output as we can get. The OPA2830 is probably the best performance and THS4281 is lower power but not dual. Both are potential candidates.

Thank you so much for following up on this and bringing the response back here.

I have been working on a circuit modeled after the evaluation board, but with 25 ohms instead of 50 ohms to keep entirely within compliance. I think that the dual-op-amp design suggested in the reply will be better.

I am working on firmware for my board at the moment, which is why my reply was delayed. I will look into the suggested circuit soon, and if I have any questions I will follow up on HFAMP as suggested.  In addition, I will verify the answer as soon as I have it implemented.

I like the 2 amp design, but one question remains which is specific to the THS5671. Page 19 of the spec gives 1.25 V as the positive output compliance, but then qualifies this by saying that "The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not exceed 0.5 V" - and thus my inclination is to alter the suggested 2 amp design to cut the virtual ground voltage in half and then double the gain on the second stage.

I'll move to HS Amp for clarification on the amp circuit, but in this forum I would like confirmation that there is a benefit to dropping the voltage to 0.5 V when optimum distortion performance is a goal.

Does the full scale output current affect optimal performance? Provided the output voltage is kept within the compliance range, does it matter whether the output current is at the 2 mA FS or 20 mA FS end of the available range?

My reading of the specification seems to imply that only voltage is important for optimal performance, not current.

I started with the suggestion from HS Amp group, chose the OPA2830, and then decided to change the resistances to adapt to 20 mA full-scale output at 0.5 V from the DAC for optimum distortion performance. I simply changed the resistor divider to produce ~0.5 V instead of ~1.0 V and then adjusted the gain to maintain 0.127 V to 4.82 V output.

My new values are R2 = 9.09k, R3 = 46.4, R4 = 1k, R5 = 1.87k, Rtia = 18.7, RG = 46.4, RF = 523.

TINA-TI seems to show a flatter response, and since DC offset at the final stage is not an issue for my circuit (capacitive coupling), I think this will work fine. If anyone cares to take a look at SPICE and tell me if I missed something, please do. At any rate, the circuit should work even if I have to change resistor values after testing.