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TVP7002 and 1080p 24/25/30

hdfactor
Prodigy 220 points

Other Parts Discussed in Thread: TVP7002, LMH1981

Hi,

I would like to add component video support for 1080p24 /25 /30 to my system using the TVP7002, however the datasheet(page 12) states that is does not support v.freq rates less than 40Hz ....

Ive tried setting the PLL etc in the hope that it is possible regardless of the datasheet... but no luck so far (it just doesnt lock properly) .... does anyone have any suggestions of how to implement support for these lower frame rates using the 7002?

Thanks, Aran.

  • 0
    Prodigy 220 points

    Any suggestions anyone? Is it possible to implement component 1080p24/25/30 with the TVP7002?

  • 0 in reply to hdfactor
    Prodigy 125 points

    Hi Aran,

     

    I'd like to know the answer to this too as these are common component standards and it's hard to understand why the 7002 doesn't support them.

    Would it be possible to derive an external clock via PLL and use this as the ref for the TVP7002?

  • 0
    Prodigy 10 points

    I also want to know than tvp7002 can supports 1080p25 input .

  • 0 in reply to wei yan
    Prodigy 225 points

    For resolution 1920x1080x30Hz I've configured tvp7002  as follows:

    //TVP7002
    WR_REG,TVP7000,0x01,0x01,0x89 // PLL DIVMSB 2200
    WR_REG,TVP7000,0x01,0x02,0x80 // PLL DIVLSB
    WR_REG,TVP7000,0x01,0x03,0xe0 // PLL CONTROL
    WR_REG,TVP7000,0x01,0x04,0x80 // PHASE SEL(5) CKDI CKDI DIV2
    WR_REG,TVP7000,0x01,0x05,0x06 // CLAMP START
    WR_REG,TVP7000,0x01,0x06,0x10 // CLAMP WIDTH
    WR_REG,TVP7000,0x01,0x07,0x25 // HSYNC OUTPUT WIDTH - 37
    WR_REG,TVP7000,0x01,0x08,0x3C //Blue Fine Gain
    WR_REG,TVP7000,0x01,0x09,0x3C //Green Fine Gain
    WR_REG,TVP7000,0x01,0x0A,0x3C //Red Fine Gain
    WR_REG,TVP7000,0x01,0x0E,0x24 // SYNC CONTROL HSout+ VSout+
    WR_REG,TVP7000,0x01,0x0F,0x2E // PLL and CLAMP CONTROL bit0 (0= HSPO by chip)
    WR_REG,TVP7000,0x01,0x10,0x58 // SOG Threshold-(RGB Clamp)
    WR_REG,TVP7000,0x01,0x11,0x40 // Sync Separator Threshold
    WR_REG,TVP7000,0x01,0x12,0x01 // PRE_COAST
    WR_REG,TVP7000,0x01,0x13,0x00 // POST_COAST
    WR_REG,TVP7000,0x01,0x15,0x04 // Output Formatter

    WR_REG,TVP7000,0x01,0x17,0x10 // MISC Control 2 AVID out, Enable Outputs
    WR_REG,TVP7000,0x01,0x18,0x01 // Clock polarity

    WR_REG,TVP7000,0x01,0x19,0xAA // INPUT MUX SELECT, RGB CH3 selected
    WR_REG,TVP7000,0x01,0x1A,0xCA // INPUT MUX SELECT, EXT REFCK, HSYNC_A and VSYNC_A selected, SOG and Clamp Filter
    WR_REG,TVP7000,0x01,0x21,0x15 // HSOUT START
    WR_REG,TVP7000,0x01,0x22,0x00 //

    WR_REG,TVP7000,0x01,0x26,0x80 // ALC RED and GREEN LSB
    WR_REG,TVP7000,0x01,0x28,0x53 // AL FILTER Control
    WR_REG,TVP7000,0x01,0x2A,0x87 // Enable FINE CLAMP CONTROL
    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL-SOG ON
    WR_REG,TVP7000,0x01,0x2C,0x80 // ADC Setup
    WR_REG,TVP7000,0x01,0x31,0x18 // ALC PLACEMENT
    WR_REG,TVP7000,0x01,0x35,0x00 // VSout Align
    WR_REG,TVP7000,0x01,0x36,0x02 // VSync Bypass
    WR_REG,TVP7000,0x01,0x3D,0x06 // Line Length Tolerance (Pixel Tolerance)

    WR_REG,TVP7000,0x01,0x40,0xFA // AVID Start 506 (496+10)
    WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start
    WR_REG,TVP7000,0x01,0x42,0x3A // AVID Stop 2106 ((506 +1600 )
    WR_REG,TVP7000,0x01,0x43,0x08 // AVID Stop
    WR_REG,TVP7000,0x01,0x44,0x01 // VBLK F0 Offset (1)
    WR_REG,TVP7000,0x01,0x45,0x01 // VBLK F1 Offset
    WR_REG,TVP7000,0x01,0x46,0x32 // VBLK F0 Duration 50 lines
    WR_REG,TVP7000,0x01,0x47,0x32 // VBLK F1 Duration

    It works fine when synks are separated (VGA format). For component (synks on the Y) it needs using of an external synk separator (lmh1981, etc)