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ADS7263

marc gaddis
Prodigy 30 points
Other Parts Discussed in Thread: ADS7263

Hello,

I am trying to interface with an ADS7263 using an ACTEL FPGA and I am not having much luck with it.  I am pretty sure that I am able to program the registers, but I cannot get the device to convert properly on the SDOA and SDOB pins.  Here is a little more info:

The ADS7263 is hardware hardwire configured for Manual Mode M0=0, M1=0, i.e. Mode1.

The CS is hardwired to 0.

VCCD – 3.3V

VCCA – 5.0V

Clock input frequency – 12.5 Mhz

VinA0 – 0V, VinA1 –  5V, VinA2  –  FloatV, VinA3  – FloatV

VinB0 –  FloatV, VinB1 –  FloatV, VinB2 – 2.5V, VinB3 – 2.5V

 

RD and CONVST are always coincident and pulses separated by 20 clock pulses (rising edge clocked).

SDI clocked-out (rising edge clocked) MSB first “after” the falling-edge of RD/CONVST pulse.

Start-up sequence:

RESET_ADC - b"0001_0000_0000_0100";

CONFIG_REFDAC_1 - b"0001_0000_0110_0010";        PDE = 1, CID = 1

REFDAC1_REG_C - b"0000_0001_1111_1111";

CONFIG_REFCM - b"0001_0000_0110_1100";

REFCM_REG - b"1111_1111_0000_0000";

After configuration

REFIO1 – 1.65Volts

REFIO2 – 2.85Volts

CONFIG_REG_DORMANT –  cycles through pattern below

                                                b"0000_0000_0000_0000";

                                                b"0100_0000_0000_0000";

                                                b"1000_0000_0000_0000";

                                                b"1100_0000_0000_0000";

 

 

Busy appears normal and good 18 clocks after read.

When CID is 0 and CE is 0, the first two leading bits are 00 as expected.

When CID is 0 and CE is 1, the first two leading bits alternate 00, 01, 10 and 11 as expected.

 

VoutA – frozen with 10000000000000 0volts

VoutB – frozen with 01111111111111 5volts

 

  • 0
    TI__Guru**** 182021 points

    Hi Marc,

    Can you grab a scope shot showing the relationship of SDI/SDO and your RD+CONVST to the SCLK, and then another showing BUSY with RD+CONVST to SCLK?  By your description above, it sounds like you are doing the configuration correctly.  Can you also possibly share your schematic?

  • 0 in reply to Tom Hendrick
    Prodigy 30 points

    Hi Tom,

    Thanks for the reply, I will work on collecting the data for you tomorrow to post.  I can share the part of the schematic that documents how we have connected the ADC(s).

     

    -Marc

  • 0 in reply to marc gaddis
    Prodigy 30 points

    Hi Tom,

    We got the ADC woking so that it is sending us data out of the serial ports.  The attached image illustrates one example.  The signal definitions are:

    Yellow = RD

    Green = our gating pulse.  this is where we think the 14-bit result should be based on our understanding of the datasheet

    Blue = The actual data coming out of SDOA

    Purple = the ADC clock

     

     

    Mode 1, PDE=1, ADC clock Frequency = 5Mhz

    The RD signal is being clock out for one clock duration rising edge to rising edge!

    Important: Is the MSB of SDI sampled on the first falling clock edge “after” RD returns to logic low?

     

    If I am operating in Mode1 with PDE=1, CID=0 and CE=1, will I see the counter operate in the leading data output stream or will it cause two leading zeros?

     

     

    Please confirm:

    1. 1.       The RD pulse “alone” activates the writing sequence into the ADC.
    2. 2.       I am to assume because register update control must be “01” when writing a preamble control word to update a register via the register update control bit field, that all the bits in the control register will be updated too.  Correct?

    If I am operating in Mode1 with PDE=1 and CID=1, will I see the MSB data bit become active at the falling edge of RD/CONVST and continue for 14-bits the pack zeros (ADS7263

     

  • 0 in reply to marc gaddis
    TI__Guru**** 182021 points

    Hi Marc,

    The screen shot did not make it through, but yes - the RD input activates the write sequence (assuming that /CS is low) on the ADS7263.  Also yes - all bits in the control register would be updated.  The MSB is going to be valid with the first falling SCLK edge after the RD is clocked into the device, MSB first through 14-bits and then zeros at the end of the transfer.