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ADS7263 How to Use

Sadanori Kato
Guru 36540 points
Other Parts Discussed in Thread: ADS7263

Hi,

We have obtained questions from our customers as follows.

Q1. Difference of Half-Clock Mode and Full-Clock Mode
What is the difference of half-clock mode and full-clock mode?
We think that the minimum data throughput in half-clock mode is about 2us,
on the other hand, the minimum data throughput in full-clock mode is 1us.
Is our opinion correct?

Q2. SDOA Only Mode
If we use SDOA only, we think that we should chose half clock mode.
Is it correct?

Q3. Full-Differential Input Mode and Pseudo-Differential Input Mode
Is it possible to set full-differential input mode and pseudo-different input mode in the same chip?
We think that we can not set both modes.

Q4. DVDD Supply Voltage Range
The supply voltage range of DVDD is 2.3V to 3.6V and 4.5V to 5.5V in half-clock mode.
On the other hand, is 2.3V to 3.6V only in full-clock mode.
Is our opinion correct?

Q5. Control of CONVST and RD
If we control CONVST and RD separately, use internal FIFO, we think that it is necessary to set the half-clock mode,
we can not use the full-clock mode.
Is our opinion correct?

Q6. Use two ADS7263
If we convert 4 input analog channel to digial values in the same timing by using two ADS7263,
can we read them from SDOA only?
We think that we can read them by using internal FIFO, controlling CONVST and RD separately and choosing each devices by CS.
Is our opinion correct?


Please tell us about them as soon as possible.

Best Regards,
Kato

  • 0
    TI__Guru**** 182021 points

    Hi Kato,

    The basic difference between Full and Half clock mode is where you read the conversion results.  In half clock mode, a conversion is underway while you are reading out the previous conversion results.  In full clock mode, you process the conversion and then read data out of the device.  The clock speed in full clock mode can be up to 2x the clock speed for half clock mode, but all of the acquisition times/conversion times are also doubled, so the throughput remains constant at 1Msps maximum. 

    A2) Full clock operation is not supported in Mode II or IV. 

    A3) There is only one option for setting Pseudo Differential mode, it is 'all or none', you cannot set the A and B channel pairs into both full differential and pseudo differential modes at the same time. 

    A4) The DVdd supply must be in the range of 2.3 to 3.6V for full clock mode operation.

    A5) You can control RD+CONVST separately in either full or half clock modes, in full clock mode though, you must have them applied separately.

    A6) Yes, this should work.  You can have a common CONVST to two devices and then apply a /CS+RD to each individually to read the conversion results.

  • 0 in reply to Tom Hendrick
    Guru 36540 points

    Hi, Tom-san,

    Thank you for your information quickly.
    We have a additional question about Q1.
    If we chose the half-clock mode, we can obtain the conversion "n" result after 40 clock cycles.
    On the other hand, if we chose the full-clock mode, we can also obtain the conversion "n" result is obtained after 40 clock cycles.
    The maximum operating frequency is 20MHz(half-clock mode) and 40MHz(full-clock mode) in each mode.
    We think that because the time obtaining the conversion result of the same input signal is different, therefore the sampling rate of the half-clock mode and the full-clock mode is different.
    Is it wrong?
    Could you please tell us about it as soon as possible?

    Best Regards,
    Kato

  • 0 in reply to Sadanori Kato
    TI__Guru**** 182021 points

    Hi Kato,

    Half clock mode is described in detail in Figure 1 on page 9 of the data sheet.  The figure depicts conversion 'n' taking place while the conversion results from cycle n-1 are being presented at the serial data output.  The throughput here is defined as tconv+tacq with a maximum clock speed of 20MHz; so there are 20 clock cycles in total which is 1MSPs.  Figure 2 is a depiction of full-clock mode, where the conversion 'n' and data 'n' are presented.  Here you have 40 clocks at 40MHz, so throughput is still 1MSPs.  If you were running in half-clock mode and only pulsed CONVST and then wait until after the BUSY output went low to read the conversion results, you would be running at a throughput of ~500k.

  • 0 in reply to Tom Hendrick
    Guru 36540 points

    Hi, Tom-san,

    Thank you for explaining in detail.
    We understood as follows.
    If the half-clock mode and full-clock mode are the maximum clock speed,
    these conversions "n" start in same timing, these input datas "n" are same,
    we will obtain the output data "n" after 1us in full-clock mode.
    On the other hand, we will obtain the output data "n" after 2us in the half-clock mode.
    Because the clock frequency is different, the sampling rate is also different.

    We will lend ADS7263 EVM board to our customers.
    If we obtain any question from customers, could you please advice to us?
    Thank you so much.

    Best Regards,
    Kato