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Other Parts Discussed in Thread: ADS5281


How can we at know what time should we latch the output data after we power up the A/D converter ? how many clock cycles of adclck does it take soon cs goes high ?I am confused about this topic total power up sequence and reset timing of ADS5281 ?

ADCLK is which we input , so it means its the clk runs everytime ? so here at particular time adclk begins ? what happens before why ADCLK hasnt started before?Can anyone help on this regard ?


HOW can we determine at partcular ADCLK cycle device is ready for conversion?/

i Appreciate u in advance


sahitya venkatayogi

  • Hi,

    In general, PLL synthesizer is configured first after supplying power in a system, and after this, other devices are configured. The main sampling clock to ADS5281 should be running before sending RESET and CS from your host. This figure illustrates the suggested timing from your RESET and CS for the timing of valid data output.