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THS5651A- Help/Question for layout signals.

Pedro R
Prodigy 70 points

Other Parts Discussed in Thread: THS5651A, SN74ALVC08, CDCE62005, DS92CK16, SN65LVDS104

I have create a layout for code testing base on THS5651A connected to a CPLD to 100 MHz clock. But I am getting wrong output.

The connections very simple:

10 digital lines with serial resistor 33 ohn.

clock 100Mhz  also with a serial resistor to 33 ohn

"Sleep", "MODE" to digital ground

Digital supply a capacitor o.1 uF to digital ground

COMP2 to a capacitor 0.1uF to analog ground

Analog supply to capacitor to COMP1

Analog supply to a 2 capacitor (0.1uf and 7.7 uF) to analog ground,

Analog supply to a ferrite to analog power supply

pot 5k to a bias and ground

extio to a 2 capacitor (0.01uF and 0.1 uF) to a analog ground

extlo to analog ground

the two output with jumper to select a connection to 50 ohn precision resistor.

The test:

The CPLD and digital same supply to 3.15 V, the analog supply to 5 V.

The clock is taken to the THS at 100 MHz,  at about 880 mVpp

The 10 digital lines at about 3.2 Vpp at  2500 ns = 2.5us

The Analog supply is taking about 5mA

Now the result is about 3 set of frequency,  i can see the clock at the output at about 100mVpp with lot of distortion

there is a set of signals at about 1.4 us signal that I cannot trigger

and there is at 2ms and 100mVpp signal very distort also.

Should I be seeing a signal at around 10 usec? also there is lot of noise and distortion, What am I missing? Thanks

  • 0
    TI__Guru* 80735 points

    Hi Pedro,

    If you could provide a PDF of the schematic and the scope shot of the output waveform showing the distortion problem, it will help speed up the debugging process.

    The clock input of 880mVpp seems low. The clock input should be at CMOS level with threshold level above DVDD/2. Please try increase the clock input and see if this improves the noise issue. 

    The THS5651A EVM schematic shows a CMOS buffer for the clock line. Perhaps you can add it into your next design to increase the clock amplitude.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 70 points

    Hi Kang,

    Before carry on I would like to ask you about the pull resistor chip on EVM (R5 R4) Could you please tell me what component is it?

    Thanks

  • 0 in reply to Kang Hsia
    Prodigy 70 points

    Regarding the clock levels, I decided not to add the buffer or outside clock generation just because I had as goal to use as few components as possible, I have here

    SN74LVC2G07DBVR but looking a inputs say 0.7*Vcc so if I am at 5 V its 3.5 volts and low 1.5 V so looking at RMS value to 880mVpp is 0.62 V that is not going to be enough right? Also looked at SN74ALVC08 and it say its at 3.6 V about 2 V so that will not work either, right? so shall be looking at amplification or outside clock generation?

    Let say I need 100 or 50 Mhz to FPGA,  65 ish to up convertor and down convertors, (I was planning to use the fpga for clock generation but maybe I should look other options) What do you suggest?

  • 0 in reply to Pedro R
    TI__Guru* 80735 points

    Hi Pedro,

    The R4 and R5 resistor pack are 33ohm series resistors, which is useful for damping out ringing in the rise/fall transitions in the data line. You can find the part # in the BOM section of the EVM user's guide: http://www.ti.com/lit/ug/slau032c/slau032c.pdf

    The clock input of the THS5651a is designed to accept CMOS level input. You may refer to page 6 of the datasheet for VIh and Vil requirements of the CMOS clock input (http://www.ti.com/lit/ds/slas197a/slas197a.pdf).

    There should be a lot of CMOS buffer with sufficient slew rate that could work fine. The SN74LVC2G07DBVR that you mentioned is open drain output, which means that you will need to tie pull-up resistors to the output for the part to function. You may select the part from the TI web:

    http://www.ti.com/lsds/ti/logic/ll-buffer-gate-products.page?paramCriteria=no

    The following part may be a good starting point. You can see that the Voh and Vol of the part have wider range than the input spec of the THS5651a. 

    http://www.ti.com/lit/ds/symlink/sn74lvc1g126.pdf

    In general, we do not recommend clocking the data converters with FPGA due to the high jitter content. You may want to clock the THS5651a with clock drivers such as CDCE62005 or LMK04800 family.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 70 points

    Hi Kang, Thanks for folllowing up here.

    After looking at your suggesting I have some question.

    without looking at start all again from a different clock source, looking at the data sheet of you suggested, you said looking at the High and low current but if you looking at the b=voltages levels I am not going to achieve it, so the question is, if you don't achieve the voltage (I think its about 2V at 3.6) would it change stage with a current level supplied? It sounds very odd, I have not look at the inside topology but it sounds very off it with change output stage with a current value?

    Also looking at fixing this voltage issue I came a cross to DS92CK16 and SN65LVDS104 for reading to the Datasheet it does for the differential to the input about 200 mV to SN65.. and less to DS92 to if I tide clock - to ground and having 800mV different should this work?

    Thanks

  • 0 in reply to Kang Hsia
    Prodigy 70 points

    Today I had time to implement another test, I divided the clock by 2 so use a DAC clock to 50 Mhz and I used this signal to create the the 10 digital signal divided by 10 bits counter so so I divided 50M by 256 giving a signals High about 2.5 us and 2.5 us Low. My understanding I should have a out a signal of about 5 us period, right?

     

    The test: (Same hardware)

    The 50 Mhz Signal is now about 2.8 V so should be enough!

    But the output I still see signals at 100 M region and us (where should be the desired) and  ms at about 100mV.

    Also I remembered that EVM use a 0 ohn resistor to tide Analog ground to Digital, right? I did also tested it with attaching both grounds together and it improve but I dont think its good enough.

    Can I see you the pictures and files through an email?

  • 0 in reply to Kang Hsia
    Prodigy 70 points

    Also Adding to my previous post:

    Looking at the Datasheet (THS5651A) page 5 say fCLK minimum 70 MSPS , Does it mean will not support 50 Mhz clock? Thanks

  • 0 in reply to Pedro R
    TI__Guru* 80735 points

    Pedro,

    I would like to clarify again that the clock input is a CMOS level input. I do not believe the LVDS drivers that you mentioned above would help the situation. The best way is to use clock drivers with CMOS output to drive the THS5651a. 

    I also want to clarify the threshold level of the clock input. We specify VIHmin and Vil_max specification for the clock input. At 3.3V DVDD, the VIH_minimum value is 2.1V. This means any input voltage that is *higher* than 2.1V will be recognized as a high logic. VIL_maximum value is rated at 0.9V. This means any input voltage that is *lower* than 0.9V will be recognized as a logic low. This is a fairly standard CMOS level threshold.

    The DAC Fclk maximum rating is specified at 70MHz minimum with DVDD of 3.3V. This means the DAC is tested at production all the way up to 70MHz. Therefore, 50MHz input clock will work. 

    Regarding your testing, please make sure your data input to the DAC matches the two's complement or offset binary code setting. I cannot see the plot that you have uploaded. Please upload the file again. If you have both time domain and frequency domain plot, it will be helpful.

    -Kang