• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 483 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Weird Conversion with ADS62P44

Devin Smith
Prodigy 20 points
Other Parts Discussed in Thread: ADS62P44

Hey Everyone,

I've been working on reverse engineering the hardware configuration for a USRP N210 radio and have run into an issue with the receiver ADC (an ADS62P44). I've attached images of the ADC output as seen by the FPGA (a Spartan-3ADSP XC3SD3400A).

The ADC is running at 100MSPS and driven by a 100MHz LVPECL clock. It's outputs to the FPGA are configured to be CMOS, 2's-complement. I have tested the transmission between the ADC and the FPGA using the ADC's built in test modes and they work 100%, this problem does not manifest. I've also verified via oscilloscope that the analog input to the ADC is correct.

The signal seems to plateau at points as if it were clipping but then it behaves normally. It also seems that some of the bits just randomly switch on and off causing large spikes to appear.

Has anyone seen this sort of behaviour before? Or have any suggestions for a solution?

Thanks, any help would be much appreciated.

---- Images ----

Input is a sinusoid at 200kHz (not sure on Vpp as I need to calculate the RX Gain)

The blue is the A channel and red is the B channel.

No Input

The blue is the A channel and red is the B channel.

  • 0
    TI__Expert 8895 points

    Hi,

    Can you please measure VCM of ADS62P44 device? It should be 1.5V with internal reference mode. When external reference mode, the differential input voltage corresponding to full-scale is given in equation 2 shown as below from datasheet,

    Full-scale differential input pp = (voltage forced on VCM) x 1.33

    In this mode, 1.5V common mode voltage to biad the input pins has to be generated externally.

    With two's complement format, you should have sampled output ranging -8192 to 8191.

    Thanks,

    KW

  • 0 in reply to KW Nam
    Prodigy 20 points

    Hey,

    So I measured VCM and it's sitting at 1.5V (1.535V to be exact) and the ADS62P44 is configured to use the internal reference.

    Yes, I have used the ADC test mode to verify that the FPGA is decoding things correctly and I get the full range of 2's complement. This problem only manifests when I try and convert an analog signal.

    I've also tried enabling the DSP blocks inside of the ADS62P44. My waveform is still heavily distorted but the discontinuities do get smeared out (slightly). This suggests to me that the signal is getting distorted somewhere in the Sample & Hold or the Quantizer. Varying the input signal strength doesn't impact these discontinuities either.

    Cheers,

    Devin

  • 0 in reply to Devin Smith
    TI__Expert 8895 points

    Hi,

    Below is the captured screen of 300KHz of analog input at 100MHz of clock rate from ADS62P44EVM. Your capture screens looks very noise with severe offset. In general, random noise does not contribute that much from the screen of your "No input" case. Are you using series damping registers to ADS62P44 device? Can you send me your schematic to me (k-nam@ti.com)? I can take a look at it.

    Thanks,

    KW

  • 0 in reply to KW Nam
    TI__Expert 8895 points

    Hi, Devin

    As the issue has been resolved, I'll close this on the web.

    Thanks,

    KW