DAC8871 Slew rate

Updating this for future readers:

There are a few things in play here.

A critical detail of all of this is that the bill of materials shows U2 as an OPA277 while the schematic seems to indicate an OPA211. Double-checking on the EVM I found that U2 is populated with an OPA277. Thanks for bringing this to our attention, I'll need to go back and fix this. As it concerns your issue at hand, though...

The datasheet specification shows 40V/us slew rate for the unbuffered voltage output, V_OUT, of the DAC8871. The measurement made at J1.2 is the output of the OPA277 installed at U2. The OPA277 is an excellent dc operational amplifier, but it's slew rate is only 0.8V/us, so the signal you see at J1.2 is limited.

When you probe J1.6 you're looking at the node that is the OPA277 non-inverting terminal and the Vout pin of theDAC8871. The DAC8871 output at the OPA277 non-inverting terminal is going to attempt to slew at 40V/us but the signal at the inverting terminal is controlled by the OPA277 output and its only going to slew at 0.8V/us. A lot of amplifiers feature back to back diodes to protect the input stage from excessive differential voltages, as illustrated below:

Since the signal at the non-inverting terminal is moving so much faster than the signal at the inverting terminal, the diodes will eventually forward conduct, shorting the OPA277 output to the DAC8871 input and creating the effect that you've observed. 

To measure the DAC performance alone you need to disconnect the OPA277 non-inverting input from the DAC8871output. To improve the performance of the whole system you need to replace the OPA277 with a faster amplifier.

Armando,

Thanks for sharing those details.

In summary:

• The goal is to create a 400kHz square wave (10 volts peak to peak? Swings from 0-10V?)
• The screen captures you have delivered are of 200kHz square waves
  • One capture seems to be using a 10 volt reference, swinging 10 volts peak to peak, from 0 to 10 volts
  • The second seems to be using a 5 volt reference, swinging 5 volts peak to peak, from 0 to 5 volts
• Let me know if I've got any of this wrong now, I'm not familiar with your scope and I'm not sure if I've identified the correct zero crossing
• The complaint is concerning the "rounded edges" of the square wave

We created a quick setup here to recreate this. Only difference is we're sweeping from -10V to +10V. You can see similar rounding on the corners:

Armando,

I apologize for my late response.

Armando Govea said:

It was added two tantalum capacitors to VREFH y VREFL signals. I mean It was added one tantalum capacitor to C14 in parallel and other tantalum capacitor to C11 in parallel.Both tantalum capacitors are 10uf, 25V. Is this the action that you recommended?.

The value of the capacitor I used was relatively arbitrary. The idea is just to add some "charge well" to the VREF_H and VREF_L lines to help source current during the very fast slew period of the DAC output.

Armando Govea said:

* Both signals do not stay at the frequency that was programmed in the DXP, the signal at 200KHz, shows a signal at 166.69KHz and signal programmed at 400KHz, shows a signal at 249.91Khz. Is it needed to add at DAC output an OPAM at its Vout pin, in order to get the right frequency?  

This is a digital problem, not an analog problem. If you probe the SPI bus of the EVM you'll see the SCLK is set to 20MHz. Each frame contains 16 bits of data and there's about 200 nanoseconds of time all together between the falling edge of CS and the first SCLK, the final SCLK and the rising edge of CS, and the total time CS spends high (this time doesn't change based on SCLK). We need at least two updates to create a square wave, so we can an equation that describes the frequencies we can achieve based on the frequency of SCLK, f_SCLK, and the number of updates per period, n (must be a multiple of 2 to maintain 50% duty cycle):

So with a 20MHz clock the fastest we can go (purely based on digital I/O, not analog settling time of the DAC), is 500kHz. If we're to keep a 50% duty cycle then we can only increment n in multiples of two to change the square wave frequency. Here's a short table of what that works out to be:

Possible Output Square Waves w/20MHz SCLK

Possible Output Square Waves w/38MHz SCLK

This is just with the EVM setup. Of course, in your own system, you wouldn't have to provide more than two updates per period of the square wave to realize this square wave. DXP just always provides back to back updates.

Armando Govea said:

* Do you have a circuit ready to test, that generates square waves (and all other standard waves) at 400KHz as maximum frequency?.

I do not have such a reference design on hand at this time. It's something that we can look into sometime in the future, though.

Armando,

First, find where the device files are stored on your PC. DXP uses special paths defined on each PC to decide where is appropriate to store it's device files. Go to the root installation directory for the DXP program, on Windows 7 this is usually C:\Program Files (x86)\DXP\. Open the file "dxp.ini", it should look like this:

[DXP]

Version =2.0.0

Build =53

DXPIndex =C:\Program Files (x86)\DXP\Misc

DXPDevices =C:\Users\Public\Documents\DXP\Devices

FWDir =C:\Program Files (x86)\DXP\fw

SaveDir =C:\Users\Public\Documents\DXP\saved

MiscDir = C:\work\dxp_v2\misc

ImagesDir =C:\Program Files (x86)\DXP\images

ClearCommLog = "TRUE"

ClearDataDump = "TRUE"

viSearchPath = C:\Program Files (x86)\DXP\Common Files\*

[LINKS]

DXPHome = http://www.ti.com/dxp

ProductFolderBase = http://www.ti.com/product/

UserGuideBase = http://www.ti.com/tool/

PDCForum = http://e2e.ti.com/support/data_converters/precision_data_converters/default.aspx

The parameter called "DXPDevices", highlighted in yellow above, is what you're interested in. If you go to that location on your PC you can view all of the xml files for the devices installed on your PC. Modify the DACXXXX XML file to change SCLK frequency. Here's an example with the DAC7311:

<?xml version="1.0"?>

<device>

  <name>DAC7311</name>

  <revision>1.0.0</revision>

  <date>21Aug2012</date>

  <devicesettings>

    <instructionwidth>16</instructionwidth>

    <channels>1</channels>

    <format>sbinary</format>

    <dataword>CCDDDDDDDDDDDDxx</dataword>

    <commanddefault>0</commanddefault>

    <commandlatch>0</commandlatch>

    <maxupdaterate>1000000</maxupdaterate>

    <interface>

      <type>spi</type>

      <polarity>1</polarity>

      <phase>0</phase>

      <maxsclk>20000000</maxsclk>

      <framebits>16</framebits>

    </interface>

    <latchpin>

      <feature>0</feature>

      <pulsepol>0</pulsepol>

    </latchpin>

    <FSplus>4.096</FSplus>

    <FSminus>0</FSminus>

  </devicesettings>

</device>

You want to change the parameter called “<maxsclk>”, highlighted in yellow above, to change the SPI clock for the device. The maximum SCLK for the MMB0 should be 50MHz. You may not get EXACTLY the frequency you type in. The DSP firmware will configure the SCLK to the closest value the clock divider will allow it to get to.

 Hope this helps. Let me know if you have issues.