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ADC803E digital output variation w.r.t. variation in the clock frequency/pulse width

Anand Kumar2
Prodigy 10 points
Other Parts Discussed in Thread: TMS320VC5402

We are using ADS803E ADC in one of our products to convert analog voltage (varying from 0-5V) to digital data for the DSP TMS320VC5402. The ADC clock is derived from FPGA through inverter 74ACT04. During normal condition, the clock frequency is 4MHz and duty cycle 50%. During the fault condition, we have observed the clock frequency varying to 3.1MHz and pulse width varying to 180ns. Is the clock frequency / pulse width variation like the one observed below, will have any impact on the digital output data of the ADC? If there is any effect, then how to quantify the ADC output variation w.r.t. clock frquency/pulse width variation?

Attached are the waveforms depicting the clock pulse and ADC enable during the fault condition. Request your response asap. Thanks in advance.

  • 0
    TI__Mastermind 29220 points

    Hi,

    Having a variation in sample clock period is not the usual usage case for a device like this and I could not begin to predict all of the ramifications of having a long clock period as you are seeing.  And the design team for this device is no longer available to consult with as this is an old device from a business acquisition years ago.

    In the best case, the device would simply take the sample of the analog input at the time of the clock edge, whenever the rising edge of the clock happens.  But since this is a pipelined device, there is a latency through the ADC of 6 clock cycles and this device does not provice an output clock with the sample codes.  The ADC expects you to use a copy of the sample clock to register the sample data into whatever device is there to process the sample data.  A long clock period should simply make the data take a bit longer to get through the ADC to the outputs and you should still meet timing into the follwing device, but i could not guarantee that.

    If you are expecting a certain SNR or ENOB for the sample data then a variance in clock period will hurt your effective SNR greatly, but if this is a time domain type of application like detecting a pulse or measuring a voltage level, then i think the clock period variation might not be a killer.  But that evaluation would be up to you, really.

    I don't know what your signal ADC enable would be, though.  i don't see such a signal pin on the device definition.

    Regards,

    Richard P.