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TSW1200EVM FPGA Source Code Request

Other Parts Discussed in Thread: ADS62P44, AFE5808A, AFE5808


I am using ADS62P44 ADC chipset.

We are considering TSW1200EVM order and I am surveying the modification of TSW1200 Xilinx FPGA code.

Please send me a FPGA verilog source code.  (e-mail : )



Dong-yong Lee.


  • Sent to the address provided.


    Richard P.

  • Thank you for your quick reply and codes.

    And I appreciate your kindly comment for source codes.


    Best regards,


    Dong-yong Lee.

  • Richard Prentice, We have accidentally erased XCF16P.

    Please send me a FPGA verilog source code and all necessary files to restore firmware to work with:

    TSW1200EVM (REV C)

    ADS5483EWM (REV B)

    ADS6445EWM (REV A)


  • Hi,

    I have been out of office so I apologize for the delay.

    if you just need to reprogram the eeprom, attached is a zip file of the batch file and folder that we use to program the eeprom when the TSW1200 is manufactured.   The batch file uses a cmd file that runs the Xilinx programmer and formatted mcs file for the eeprom is included.  The two bit files are included as well.  The batch file was developed way back for the ISE tools version 9.something, so the path names might need to be fixed to make the batch file work for newer Xilinx tools.  Or you can program the mcs file into the eeprom manually.

    This would be much safer than trying to make the bit files again from source code.


    Richard P.
  • Hi:

    I have the sense I've stepped off a high cliff here (I'm VERY new to Xilinx FPGA coding....) and the sharp rocks at the bottom are rushing towards me.

    I have inherited a project that needs to tie three of TI's octal high speed ADC's (ultimately the ultrasound AFE5808A series) to a Xilinx FPGA (TBD) but have no reference designs to looks at as to how to accomplish the LVDS connection, deserialization and capture (ideally into a dual-ported FIFO).

    The TSW1200EVM seems to do much of this, are the Xilinx design project files available to use as a starter point?
    Also, any supporting design rationale documents that would assist understanding the structure would be appreicated.
    I am aware that there is a TSW1250 board that interfaces with the AFE5808A dev board, so if the same kinds of Xilinx design files and support docs for the TSW1250 exist, those would be very nice to get as they would show how to handle the other functions included in the AFE's.

    My bigger problem is that TI has migrated away from Xilinx FPGA's in their latest deserializer boards, which is okay if we were starting fresh.

    But I'm constrained to sticking with Xilinx FPGA's....

    If this conversation is bigger than should go on in this forum, please contact me at curtis(@), with the brackets removed from the email address.



  • Hi:

    I have been reading another thread related to FPGA code for the TSW1400EVM and after much discussion here, I have managed to shift opinions about our somewhat arbitrary Xilinx (vs Altera) project constraint.

    If the Altera Quartus project code for the TSW1400EVM was available, in a version that supported (or came close to) supporting the AFE5808 style LVDS connection requirements, there would be much rejoicing on this end.

    Is this Quartus project code available?