ADS803E Clock input circuit configuration

Ganesh Moorthy

Other Parts Discussed in Thread: ADS803

Hello Team,

One of our customer needs the input circuit configuration of the clock input pin for the ADS803E device (input impedance details). Atleast for a similar kind of device.

Thanks and Regards,

Ganesh.S

over 11 years ago

0 Tom Hendrick over 11 years ago

TI__Guru**** 180021 points

Hi Ganesh,

Not sure who moved this query to the Precision Forum, but it was in the correct spot. The ADS803 belongs in the High Speed BU. The DWIN Hierarchy on this device is: HPA==>HSP==>HSP DC.

This is one of those 'grey area' parts that fits between the PA and HSP BUs. I'll move it back to the HS forum for you.

0 Jim Brinkhurst1 over 11 years ago in reply to Tom Hendrick

TI__Mastermind 44680 points

Hi Ganesh

The CLK input is a CMOS logic gate input. Per the datasheet the typical gate capacitance is approximately 5 pF. The logic thresholds are listed in the Digital Inputs section of the datasheet specification table.

I have looked but I don't believe there is any additional information available for this pin. At 5 MHz CLK rate, the frequency is low enough that a more complex model is not really necessary. This part was released before IBIS modeling was typically provided for data converters.

I hope this is helpful.

Best regards,

Jim B

0 Ganesh Moorthy over 11 years ago in reply to Jim Brinkhurst1

TI__Prodigy 550 points

Hello Jim,

Thanks for your reply.

Regards,

Ganesh.S

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ADS803E Clock input circuit configuration