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Xilinx FPGA with ADS5282EVM

Tariq Siddiqui
Expert 2270 points
Other Parts Discussed in Thread: FMC-ADC-ADAPTER, ADS5282

Hi,

TI page says:

FMC-ADC-ADAPTER provide direct connection to FMC connectors on Xilinx series 6 and series 7 FPGA evaluation and development kits for over 80 TI high speed ADC and DAC EVMs.

I couldn't figure out if FMC-ADC-Adapter provided by TI has has LPC interface or HPC. 

Can you tell me which Xilinx Series 6 FPGA EVM can be interfaced with ADS5282 EVM via FMC adapter ?

I really need to know this as soon as possible.

Thanks.

Tariq

  • 0
    Expert 2270 points

    Is it really impossible to get answer to my query ?

    -Tariq

  • 0 in reply to Tariq Siddiqui
    TI__Mastermind 29220 points

    Hi,

    I do not know all the differences between the LPC adn HPC.  Physically, I believe the adapter board will connect to either one of them and that the main difference between the LPC and HPC is the number of signals available.  The physical design database for the FMC-ADC-adapter is available on the TI web and you would need to consult the schematic page in that to find out which ADC EVM signal is conencted to which pin of the FMC connector so that you could begin to edit your constraint file to reflect what FPGA pins the data comes in on.   I suspect you would find that after you trace the signals from the ADC EVM through the adapter board to the FMC connector that either of the FMC connectors would work, but I don't know that.  We don't *have* one each of every development platform here in our facility to check all possible combinations.  The FMC-ADC adapter board was developed with a Xilinx representative telling us what FMC pins we should connect all of our signals to - and that was done with a Virtex 5 development platform in mind at the time.

    The ADS5282 EVM Users Guide http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slau205&fileType=pdf on page 24 shows the pin assignment into the EVM connector. 

    The schematics for the FMC-ADC-adapter http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=slor101&fileType=zip show the mapping from our EVM connector to the FMC connector.  After it connects to your development platform at the FMC connector, you will have to see what FPGA pins the signals end up at so you can 1) all the signals from the FMC get to the FPGA 2) edit your constraint file 3) make sure the bit clock arrives at a clock capable input 4) all the other signals go to a bank of IO that is served by that clock.  i believe the ML605 development platform would have no issues, but I can't say that development platforms for other Xilinx products haven't changed the FMC pin assignments.

    Regards,

    Richard P.