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Connecting DAC1280 to a MCU

Other Parts Discussed in Thread: DAC1280

Hi

Our customer is planning to use DAC1280 in thier application.
We are confused with the signal connection from the Controller.

As described in this E2E post, we are confused about how to generate the
"SYNC" signal to the DAC1280.
Is the SYNC Signal necessary to control the DAC1280?

According to the Datasheet of DAC1280, it says
"When SYNC is taken high, the DAC resumes sampling TDATA on the sixth rising
CLK edge after SYNC is high"

So I think the data from the controller(MCU) should delay 
first five clock cycles so that the DAC samples the TDATA Properly.
But it will be difficult from MCU to provide a clock delay.

Please let me know if there are any reference design connecting
DAC1280 with a MCU.

Best Regards.
Prad

  • Please let me know if there is any details on SYNC Signal and
    how to provide TDATA from MCU with clock delay.

  • Hi Prad1,

    I'm sorry for the delayed response on this. We don't have any reference designs for the ADS1280 because it typically goes into seismic applications where we don't usually get asked for reference designs.

    Regarding the SYNC signal, the ADS1280 data sheet says that you can tie SYNC high if you prefer not to use it. However, it may be beneficial to use it at first...

    TDATA is sampled every 16 clock cycles. Without using SYNC, you won't know exactly which clock will sample TDATA. Therefore, you would hold TDATA for 16 clocks before switching and holding it for the next 16 clock cycles. This operation is fine, but you're signal may be out of phase slightly with what you expect depending on when the TDATA first gets sampled.

    You may want to, instead, use SYNC initially by pulling it HIGH and then starting the clock. There is no maximum limit to the tSCSU timing, so you can start the clock anytime after SYNC goes HIGH (at least 30ns after SYNC's rising edge).

    Keep in mind that TDATA does not need to switch on the 4th and 6th clock cycles. It just needs to be valid on the fifth clock cycle. Therefore, you can start TDATA HIGH/LOW depending on your preference and switch (or hold) it's value anywhere between the 6th and 20th clock cycle.

    Best Regards,
    Chris