DAC5672A digital word intermittent data sampling error

Hi Renato,

How are you hooking up CLKIQ? A schematic would be useful. Also you want to make sure SELECTIQ is high during A-channel data transfers.

Regards,

Ruben

Hi Ruben,

I'm driving CLKIQ in phase with WRTIQ. The signals are coming directly from some FPGA pins.

The following schematic is an extract of the output stage of the FPGA design.

You can see that WRTIQ is connected to CLKIQ. We have verified with the scope that the two signals have aligned edges. CLKIQ is generated with a PLL with a defined phase shift with respect to SELECTIQ. The rising edge of CLKIQ has been placed in the middle of the SELECTIQ bit period.

RESETIQ is drived only dirung the reset of the FPGA block.

The following is the schematic of the board part related to the DAC5672A:

part

Mode is tied to GND and GSET is connected with a 1nf capacitor to GND (it has an internal pull-up).

Can you confirm me that CLKIQ and WRTIQ acts as clocks to a portion of internal DAC logic that is sensitive to the rising edge?

I've assumed that assumption was true so all the signals (DA[13..0], RESETIQ, SELIQ) setup and hold times has been maximized placing the rising edge of CLKIQ (and WRTIQ) in the middle of all the data eyes (the data change on the falling edge of CLKIQ).

Hi Renato,

I don't see any issues with your schematic or the way you have configured CLKIQ, WRTIQ, SELECTIQ and RESETIQ. As you indicate CLKIQ and WRTIQ timing is done with respect to the rising edge.

This DAC only accepts offset binary data, can you confirm the data into the device is formatted accordingly?

Regards,

Ruben

Hi Ruben,

I've found that there is a timing problem related to the delay between the WRIQ and CLKIQ signals: in my design CLKIQ is delayed of 0.35ns with respect to WRTIQ due to the FPGA and board routing skew.

We have done some tests introducing some delays on WRTIQ and we found the way to make the board behave well:

A) if the delay from WRTIQ to CLKIQ is 0.00ns than the DAC works.

B) if the delay from WRTIQ to CLKIQ is 1.80ns than the DAC works...

The problem is that we have to know which is the timing margin of our design. Can you give me some more in in depth information (more than the information present on the DAC5672A datasheet) related to the timing of the digital input data?

I mean, I think that WRTIQ rising edge will capture the signals DA[13..0], SELECTIQ and that CLKIQ rising edge  will capture the data fron the internal DAC latches (see LATCH A&B on page 2 - functional block diagram).

To correctly design the FPGA part, I need to know some thinks:

- if the data bus DA[13..0] is latched on the rising edge of WRTIQ (the data setup and hold times Tsu and Th are reported into the datasheet but it is not stated if they are relative to the WRTIQ or CLKIQ clock)

- what is the setup and hold time of SELECTIQ with respect to the rising edge of WRTIQ (if WRTIQ is its reference clock!)

- if there is a way to periodically assert RESETIQ without affecting the DAC current output analog value to prevent single events to permanently switch the 2 output channels

- what is the min and max delay from WRTIQ to CLKIQ (if CLKIQ rising edge samples the LATCH A&B outputs, than there can occur internal DAC metastability problems if the CLKIQ is slightly delayed as in my first setup)

Regards,

Renato

Hellow Hamza

There were the following questions from the Japanese customer who watched TI E2ETM Community.

Q1:The document"X2_Interleaved_Mode.pdf" is written as DAC5652, but is the inside circuit same in DAC5652A?

Q2:If there is official inside circuit document, would you dispatch it?

Q3:I feel that the contents of the datasheet are too short. Is there the plan that puts this document in datasheet?

Best regards
Keishi,Nishijima in JPIC

1- Yes! the circuit is same in 5652A. The only difference between 5652A and 5652 is that maximum voltage between AVDD and DVDD for the DAC5652 is -0.5V to 0.5V while Maximum voltage between AVDD and DVDD for the DAC5652A is -4.0V to 4.0V.

2- This was an internal document that has been released to enhance our customer's understanding of the device's functionality.

3- Unfortunately, the numbers provided in the document, though correct to the best knowledge of designers, have not been production tested according to TI standard of quality assurance and therefore, cannot be included in the datasheet.

Let us know if you have any trouble using this device and we will be glad to assist.

Regards,

-+ Hamza

Hello Hamza

I've driven the DAC5672A clk inputs using some PLLs outputs @120MHz . The outputs are delayed each other in 1/4 period steps (approx. 2.5ns) taking into account the internal structure of the data paths to the DAC output latchs. Now all works perfectly.

Thanks for te useful informations.

Renato