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TIPD120 accuracy

Other Parts Discussed in Thread: TIPD120

In one of our new designs, we are required to support upto 3 wire RTDs. 

We were looking into "TIPD120 Ratiometric 3-wire RTD Acquisition system" from TI as a reference for our design. It is mentioned in the spec of  TIPD120 that measurement accuracy is 0.005% FSR . 

Since Full Scale range of temperature is 100°C ( 0°C to 100°C), the accuracy in terms of temperature is 0.005°C.

Is the above calculation correct ? Is there a particular reason for mentioning the accuracy in terms of FSR?

Also, Is the above accuracy is guaranteed over the operating temperature range of the board ?

Thanks & Regards, 

Suresha N S

  • Hello Suresha,

    Many systems specify accuracy/error in terms of %FSR which means the accuracy in percent of the full-scale range.  We are going to update some things about TIPD120 and one of them is to specify the accuracy in degrees Celcius to make it more consistent with other temperature sensing applications specifications.  

    Your calculations are correct and after a gain + offset calibration the measured accuracy was <0.005C at room temperature.  The design was tested on several boards which produced very similar results after calibration.  

    Designs with hardware compensation resistors (RCOMP) do not typically do well over temperature without frequent calibration because the drift of the additional RCOMP resistor directly affects the measurement accuracy. 

    If the design is meant to operate over a wide operating temperature then it is advised to remove the "RCOMP" resistor and operate the system without hardware compensation to avoid the drift issues mentioned previously.  Data without a hardware compensation resistor will be the main update to TIPD120 and it will be online by the end of the year.

    Thanks for reading!

  • Dear Collin Wells,

    Thanks for your quick response.

    We had couple of queries regarding your response. It would be very helpful if you can share your thoughts on the below queries.

    • We assume hardware compensation resistor (RCOMP), you have mentioned in your response is same as Rref (In the schematic R9 with a value of 8.2K) . Is this correct ?
    • For our accuracy calculation over the temperature range, we have considered the below parameters :
      • ADC  - ADS1247IPW 
        1. ENOB - Calibration not possible
        2. INL - Calibration not possible
        3. Gain Error - Can be removed through calibration
        4. Offset error - Can be removed through calibration
        5. Gain Drift - Calibration not possible (We will be doing calibration only  @ room temp)
        6. Offset Drift - Calibration not possible (We will be doing calibration only  @ room temp) 
      • Resistor - Rref 

        1. Manufacturing tolerance -  Can be removed through calibration
        2. Temperature co-efficient - Calibration not possible (We will be doing calibration only  @ room temp)

    To find out the RTD measurement accuracy, we are calculating the RMS value of the non-calibrable errors mentioned above. Please comment if we have missed out on anything here with respect to your calculation.

    Looking forward to your response.

    Regards,

    Suresha N S

  • Hello Suresha,

    My apologies, the resistor was named "Rzero," not "Rcomp" in the paper (120 Ohms).  It's the resistor in series with the other ADC input that creates a differential signal for the ADC.  The "Rref" resistor is the resistor that creates the ratiometric reference voltage used for conversion.  If the design is to operate over a wide temperature range then the drift of both the Rref and Rzero resistors can create effects that are hard to calibrate out which is why we recommended not using Rzero if the design is to operate over a very wide temperature range.  

    The error parameters from the ADC and resistor that you've noted are correct as well as which ones you can calibrate and which you can't.  Other parameters that should not be ignored are:

    1. IDAC matching (can be mostly removed through IDAC chopping)
    2. IDAC matching drift (can be mostly removed through IDAC chopping)
    The calibration method used to produce the measured results included both a calibration of the ADC using the internal offset calibration as well as a final system level offset and gain calibration that removed the offset of the Rzero resistor and the initial gain error from the ADC and Rref resistor.  The ADC includes an integrated temperature sensor that could be used to indicate that the system temperature has shifted enough to merit performing another ADC internal offset calibration.  That would only help eliminate the offset drift over temperature and would not help with the gain drift of the ADC and Rref resistor.  If very high accuracy is required then you may consider characterizing the design over temperature to remove the gain drift.  
    If you share your calculations we will gladly look them over for correctness.
  • Dear Collin Wells,

    Thanks for your detailed response.

    Our design need to support different type of RTDs such as Pt100, Pt200, Pt500 & Pt1000. Also, we need to measure temperature from -200°C to +850°C.Thus our RTD resistance will be varying between 18Ω to 3.9KΩ. Thus it is difficult to put a single Rzero suitable for all RTD types.

    Thus we have decided to remove the resistor Rzero & build a similar circuit for our design.We have modified the TI schematics for our use case & attached below. We have also changed the current derive to 250uA. With 8.2KΩ resistor as Rref, this will result in Vref voltage of 2.05V. 

    Please let us know if you see any concerns with this circuit.

    We have done the accuracy analysis for different type of RTDs with the above circuit & attached the same with this post. We have changed the gain of the PGA depending on the input, so as to increase the accuracy of measurement. Also, as of now, we are not planning to perform a calibration over the operating temperature range. Thus the gain drift & offset drift errors are still mentioned as non – calibrable errors in our calculations.

    It would be really helpful for us if you can look into our calculation & share your thoughts.

    Regards,

    Suresha.N.S.

    RTD_Analysis.xls
  • Hello Suresha,

    Thank you for the additional information.  I agree that your system is better suited without the Rzero resistor. With only a +3.3V supply it looks like you'll violate the input common-mode and compliance specs for the IDACs if you use 250uA with an 8.2k resistor and a PT1000 RTD.  Your calculations show this in cell F67 which shows 1.952V being added to the 2.05V reference which is above the supply voltage.  Consider redesigning this system to accept a +5V AVDD supply so you can tolerate the voltage developed with the higher resistance sensors.

    I have a few other items to tend to this morning so please give me a day to look through the rest of the calculations and your circuit.  I'll reply back as soon as possible.

  • Dear Collin wells, 

    Yes. We missed out on the common mode voltage calculation of analog input. As suggested by you, we are planning to use a +5V AVDD supply. Thanks for your comment.

    We are looking forward to your thoughts on our accuracy calculations.

    Regards,

    Suresha N S

  • Hello Suresha,

    I had some time this morning to go through your calculation spreadsheet.  Here are some notes:

    Since you're looking at the IDAC matching I have to assume this is for a 3-wire RTD.  In that case the VREF voltage is 2*IDAC * RREF as described in TIPD120, so update cell C6 to show this correctly. 

    Other than that, the theory behind the rest of the spreadsheet is very sound and I believe this takes a conservative approrach to the final accuracy.  Here are some notes:

    1.)  Max offset drift you've listed in C35 is only 6uV for a PGA gain =1, the minimum PGA gain you'll be using is 2 and highest is 16.  For the higher gains the offset drift will go down resulting in less effect. 

    2.) While higher PGA gains result in less offset drift, they result in higher gain error.  The 0.03% spec you've used in C37 is only for PGA gain of 128 which you will not use. 

    3.)  You could try to reduce the effects of C47 by "chopping" the inputs back and forth as suggested in TIPD120.

    Otherwise I think you've done a great job and agree with your calculations. 

    Please let me know if we can help with anything else.

     

     

     

  • Dear Collin Wells , 

    Thanks a lot for your valuable comments.We are using 3 wire RTD & I will implement  your comment regarding VREF calculation. 

    Also, we have a new requirement of supporting Thermocouple along with the RTD on the same pins.

    For thermocouple, we are planning to use the same circuit. We will stop the current drive when thermocouple is connected & use the PGA to amplify the thermocouple voltage input. In this case we need to provide the reference voltage to ADC in some other ways.

    Does TI has a measurement circuit which supports both RTD & Thermocouple ? We would like to have a look at the architecture if there is a reference board for this.

    Regards,

    Suresha N S