Hi Team,
Please tell me in case if there is a problem, if the clock pulse for ADS7263 is not continuous.
CLK pulse is intermittent as attached.
Thank you for your support in advance.
Best Regards,
Kawai
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Hi Team,
Please tell me in case if there is a problem, if the clock pulse for ADS7263 is not continuous.
CLK pulse is intermittent as attached.
Thank you for your support in advance.
Best Regards,
Kawai
Hi Kawai,
The burst clock would be fine, but the RD input needs to see the falling SCLK edge while it is in the high state. Your diagram shows it as (essentially) high for the same period of time that the SCLK is high - if you can stretch that to a point where it is high 2x as long as SCLK, that should work.