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About a setup of DAC5688EVM & TSW1400EVM.

Guru 19495 points
Other Parts Discussed in Thread: DAC5688EVM, DAC5688, DAC5689

DAC5688EVM and TSW1400EVM tend to be used and it is going to output the following frequency.

Is it right at an attached register setup?
If a mistake occurs, please let me know.

7522.DAC5688_data.txt
Texas Instruments Inc.
DAC5688 EVM Register Configuration

DAC5688 Registers
Address	Data
00		01
01		0B
02		43
03		00
04		19
05		10
06		00
07		00
08		CD
09		CC
0A		CC
0B		20
0C		A6
0D		A6
0E		00
0F		2D
10		00
11		00
12		00
13		00
14		00
15		00
16		AA
17		10
18		80
19		00
1A		0D
1B		FF
1C		00
1D		38
1E		00

CDCM7005 Registers
Address	Data
00		005FF1F0
01		02B282DD
02		D14000A2
03		00000027

------------------------------------------------------------------------------------
[Request specification]
- Use PLL (divide ratio: x8).
- 100MHz CLK input
- DAC input are -38.64MHz by an I/Q input.
(the 13th page of the following web)
- A NCO input is 102.5 MHz.
⇒It is going to mix and is going to output 63.86 MHz.
http://www.ti.com/lit/an/slaa523a/slaa523a.pdf

※A setup of TSW1400
- It is DAC CMOS firmware download.
- Single tone 
- Center frequency: -38.64 MHz(Complex)
- 800Msps
- 2's Comp

[About a background and register data]
- There is no DAC5688EVM at hand and it measured by DAC5689EVM.
(DAC5689 is the same except that there is no PLL compared with DAC5688)
- DAC5689EVM has been outputted normally.

The GUI register data of DAC5689EVM is attached.

8156.DAC5689_data.txt
Texas Instruments Inc.
DAC5689 EVM Register Configuration

DAC5689 Registers
Address	Data
00		03
01		0B
02		23
03		00
04		19
05		10
06		00
07		00
08		CD
09		CC
0A		CC
0B		20
0C		A6
0D		A6
0E		00
0F		2D
10		00
11		00
12		00
13		00
14		00
15		00
16		AA
17		10
18		80
19		00
1A		0E
1B		FF
1C		00
1D		00
1E		00

CDCM7005 Registers
Address	Data
00		005FF1F0
01		02B282DD
02		D14000A2
03		00000027

※About the data of the question register
⇒Compared the register of DAC5688 and DAC5689, and it wrote it in order to carry out the same output by DAC5688EVM (PLL use).

------------------------------------------------------------------------------------

Thank you for your consideration.

  • Satoshi-san,

    I have modified the DAC5688 configuration file to fit the DAC5688 PLL mode. The changes are:

    1. changed the input clock configuration per page 33, table 5, PLL mode with CLKO. The assumption for this is based on your DAC5689 setting.

    2. Changed the PLL gain and PLL_range configuration in config0x1E based on the table described on page 8 of datasheet. The customer may use other range if needed, but this is the test range at the production. 

    -Kang

  • Dear Kang-san

    Thank you for the detailed reply.

    Moreover, please let me know one more point.

    LED6&LED7 of TSW1400EVM does not light up certainly.
    If there is the method of light "on certainly", please let me know.

    A situation is written to below.

    --------------------------------------------------------------------------------------------------------------------------------------------------

    Usually, a gain is set as 5 dBm for the frequency input of J20, and the setup of EVM is repeated.
    - Repeat until LED6 & LED7 light up.
    - When the light is not light up, turn OFF a power supply and repeat from the beginning.

    If the light may be switched on immediately, the light may not be switched on at all.


    Moreover, does the GUI starting turn of DAC5688EVM and TSW1400EVM influence about lighting?

    --------------------------------------------------------------------------------------------------------------------------------------------------

    Best Regards,

    Satoshi

     

  • Satoshi,

    The CMOS clock pins are set to 3.3V-LVCMOS in the firmware. The VCCIO reference voltage for the bank for these pins is at 3.0V. The minimum specified voltage to guarantee a logic "1" is 1.7V. If the clock input is lower than1.7V and greater than 0.8V, the LED may be on or off.

    Regards,

    Jim