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LM97600 SRAM Questions

Hi, 


I just had a couple of questions related to the working of the LM97600RB and the usage of the SRAM for storing the data samples. When data is being read, is it first stored in the SRAM and then when Wavevision grabs the data, is it off the SRAM or does it get it directly from the samples being captured on the ADC through the use of buffers on the FPGA ? 

Is it possible to completely avoid using the SRAM and directly send data to the PC using FPGA memory as a buffer ? 

  • Hy Syed

    I apologize for the delayed response.

    The data from the ADC is deserialized and then stored into the SRAM. When Wavevision requests a new capture of data here is the process:

    Wavevision sends a capture request to the FPGA.

    The FPGA stores the selected data size into SRAM and then stops storing data.

    The PC then starts reading the stored data out of the SRAM and continues until all data has been transferred.

    The data is then processed and displayed per the current GUI data display mode (time domain, histogram or FFT).

    Data cannot be read directly from the ADC to the PC. Since the ADC output data rate is so high the data must be temporarily stored somewhere. In some of our other ADC reference boards we do this using internal FPGA memory. On this board since we have the SRAM devices, that is the destination instead.

    It would be possible to re-design the FPGA to store only to internal memory instead of SRAM, but that would severely limit the size of the record that could be captured.

    Best regards,

    Jim B

  • Thanks for the explanation! I am not looking to store a large record just around 1000K samples such that the FPGA internal memory acts as a buffer. Would we still be able to use WaveVision after this modification by completely ignoring the SRAM on the board and just using perhaps BRAM within the FPGA to 'emulate' the SRAM ? You mentioned that there are similar designs which use the internal FPGA memory rather than the SRAM, could you please out boards which are similar to the LM97600RB or which use this kind of setup ? 

    Thanks again!
    Syed

  • Hi Syed

    Do you mean 1K (1,024 samples) or 1000K (1,024,000 samples)?

    The FPGA resource utilization report lists the following for RAM/FIFO:

     Slice Logic Utilization

    Used 

    Total

    Utilization 

     

    Number of BlockRAM/FIFO

    84

    148

    56%

     

        Number using BlockRAM only

    68

     

     

     

        Number using FIFO only

    16

     

     

     

            Number of 36k BlockRAM used

    63

     

     

     

            Number of 18k BlockRAM used

    9

     

     

     

            Number of 36k FIFO used

    12

     

     

     

            Number of 18k FIFO used

    4

     

     

     

        Total Memory used (KB)

    2,934

    5,328

    55%

     

    I think it should be possible to update the design to substitute internal RAM instead of the external SRAM and still use Wavevision. The number of samples that could be captured would depend on how efficiently the available memory resources can be used.

    Some boards that use internal FPGA memory rather than external RAM are the ADC12D1800RFRB, ADC12D1800RB, ADC10D1500RB. The design package information in the product folder for each of these boards does include FPGA source code for reference.

    Best regards,

    Jim B

     

  • Sorry, that was a typo. I meant 1K samples not 1000K samples. If I'm able to use WaveVision after the modification, that would be great! 

    I'll take a look at the boards that you mentioned and hopefully it should shed some light on how I can go about implementing the modification.

    Thanks!

    Syed