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SAR Sample and Hold

Brian Cox1
Prodigy 225 points
Other Parts Discussed in Thread: ADS7822, ADS8320, ADS8327

Hello all,

I have a question about the need for an external sample and hold circuit for certain SAR type A/D converters.

Referring to the datasheet for a part like the ADS7822 or ADS8320 http://www.ti.com/lit/ds/symlink/ads8320.pdf, the theory of operation section makes a statement about the architecture inherently including a sample and hold function.  Does this mean the chip performs sample and hold of the analog input internally and there is no requirement for or benefit from an external sample and hold circuit?

If so, how does the architecture of these parts differ in terms of the sample and hold functionality from a part like the ADS8327?  http://www.ti.com/lit/ds/symlink/ads8327.pdf

Thanks

  • 0
    TI__Expert 6925 points

    Hello Brian,

    All SAR ADCs have similar input architecture with a “sample and hold capacitor” to capture the input voltage and also perform its conversion. The external capacitor is mainly used to decouple kickback currents at the end of conversion. Let me explain more in detail.    

    First, in sampling mode (also called acquisition mode), the input is sampled connecting the “sample and hold capacitor” to the ADC input pin. This allows the “sample and hold capacitor” to hold the same voltage as the input assuming enough time is given to settle.  Then, when the conversion is initiated, the “sample and hold capacitor” is disconnected from the ADC input holding the input voltage.

    However, during conversion, internally, some of the “sample and hold capacitor” charge must be used to calculate the conversion result bits, and at the end of conversion, the “sample and hold capacitor” final value voltage is different from its initial value. This final voltage in the “sample and hold capacitor” isn't constant and depends on many variables such as input voltage, reference voltage, number of bits, and it is different for every SAR ADC.

    After the conversion is done, when the “sample and hold capacitor” is reconnected to the ADC input, charge kickback is created because the “sample and hold capacitor” is not exactly the same value as ADC input. Again, since the final value of the “sample and hold capacitor” is not constant, the charge associated with the kickback is also not constant.

    The kickback currents disturb the op-amp output that drives the ADC input increasing settling time, so an external capacitor is used to decouple the charge kickback improving settling by minimizing disturbance at the op-amp output. The external capacitor is typically sized 10x-20x times larger than “the sample and hold capacitor” to make sure that, for any charge kick back, the voltage at the ADC input pin only changes by +-10% or less.   

    Regards,
    Rafael

  • 0 in reply to Rafael Ordonez
    Prodigy 50 points

    Hi Rafael,

        Why the external capacitor is typically sized 10x-20x times larger than sample and hold capacitor?

       Could you tell me in detail?

       And the external RC filter should be selected for charge times(t=RC)   fast so the voltage of sample and hold capacotor is fast to charge to the input voltage for accuracy,Or there is difference between input voltage and acquisition voltage.

       Thanks a lot

    Robert