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About operation of DAC5687

Satoshi
Guru 19655 points
Other Parts Discussed in Thread: DAC5687, TPS51020, TPS40007

Although the customer is evaluating DAC5687, the following operations have occurred.
If a cause is known, please let me know.


------------------------------
[Phenomenon]
- Where the SLEEP pin of DAC5687 is set to High（Active), set up the register of DAC5687 by a serial signal.

When a setup is completed, a SLEEP pin is canceled (Low) and data is inputted into DAC, it may not be obtained with the time of an output being obtained from DAC.

After activating a SLEEP pin in that case, an output may be obtained if it cancels.

If this operation is repeated several times, the time of not being obtained with the time of an output being obtained will come out.

[Setup]
- As for a serial clock, 5 MHz
- TXENABLE and QFLAG are High 
- PLL VDD is GND connection.
- PLL LOCK is intact.
(It was outputted to High)

[My idea]
Input power sources are the following devices.
- DVDD(1.8V):TPS51020
- AVDD(3.3V):TPS40007
Having inputted into AVDD with the DC-DC converter, I think that the inside DAC is affected.

------------------------------

Thank you for your consideration.

  • 0
    TI__Guru* 79915 points

    Satoshi-san,

    When Sleep pin is asserted, most of the logics including clock paths inside the device may be shut-off. Upon de-asserting the Sleep pin, some logics inside the DAC such as FIFO and NCO will need to be synchronized/initialized. 

    I believe the problem that the customer is seeing is that they are not observing reliable output state when SLEEP pin is de-asserted. Please let me know if I may have mis-interpreted your questions.

    I would recommend that upon initializing/configuring the DAC, the customer set the SLEEP pin to low so it is not in low power state. The customer may set TXENABLE low during configuration so the DAC does not output transients during initialization.

    -Kang