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ADS1212 Byte Zero of CMR Register Changes To FF

Some of our customers have reported occasional sudden jumps in their data, that are cleared up by rebooting our device. These are fairly rare events. There are generally months between an event in a population of hundreds of channels.

We came up with a debug command to dump the ADS1212 register values and have correlated this with a change in the low byte of the CMR register to FF. It always seems to effect byte zero, and it always seems to change to FF. Here is a sample of our output....

Read A/D C 0 O 184 S 6309351 CMRA 4208426f CMRX 4208426f
Read A/D C 1 O 125 S 6317784 CMRA 4208426f CMRX 4208426f
Read A/D C 2 O 170 S 6316688 CMRA 420842ff CMRX 4208426f  *
Read A/D C 3 O 42 S 6312138 CMRA 4208426f CMRX 4208426f

CMRA is the Actual reading from the A/D.

CMRX is the eXpected value that was written in. The * indicates that they don't match.

Byte zero changes the rate at which the A/D operates so the zero and full scale correction values are no longer valid, hence the jump in the data.


This generally happens after many readings of the A/D, so I first suspected that a timing glitch was causing a write to the register instead of a data request. I noticed that the command to write an FF to CMR byte zero could be found in my bit pattern to read the data output registers if it is shifted by three bits, as shown in the attachment image. We changed the last 24 bits to zeros, to avoid this, but it had no effect.

We are contemplating rounding off the A/D data rate settings, so byte zero is always intentionally set to FF. That way, the event that changes the register to FF wouldn't have an effect. That may work, but it doesn't seem like an ideal solution.


Any suggestions?

Thanks

Chris

  • Hi Chris,

    Welcome to the forum!  I can see why this is frustrating.  Usually this type of event is related to some form of transient.  I think that the data output relative to the CMR setting is coincidental, although interesting.

    Can you send me some more detail as to fclk and SCLK speeds? Can you re-write the proper configuration without resetting the device?  Is this the only register that has this issue?  Do you see any other failure conditions?

    Best regards,

    Bob B

  • Hello Bob,


    Thanks for the response.

    I'm running fclk at 2MHz, and SCLK at 200kHz.

    As far as we can tell, the part still operates fine, it just runs at a new rate. We can configure the A/D without a reset. The way our software operates, though, our customers tend to issue a reboot command to clear it up.

    I agree that this is transient related. We have several customers reporting this that are using our device to measure parameters on jet engines. That's a very noisy environment that I can't duplicate in my lab.

    One customer reported that putting ferrite chokes on the inputs reduced the events significantly. His test cell was shut down for a time and the building power was updated. New transformers, etc. After that, he had no more problems.

    This is one of the strangest problems I have ever encountered. The FF is not a power on default value. We have more than one user reporting the same change to the same register. It took quite a bit of sleuthing to figure out what was happening inside the A/D, because the events are so rare.

    Thanks,

    Chris