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ADS42LB49 internal clock divider

Anil Karabeyli
Prodigy 30 points

Hi,

I will use 2 ADC42LB49 in my design and synchronization is very important for me. I am planning to using a clock generator and a clock buffer(LVPECL) to drive ADCs. Considering both timing and performance; do you advise me to use a 250 MHz clock as an input to the ADCs or is it better to use a 500MHz or 1GHz clock and divide it in ADC to 2 or 4? What will be the difference?

Also it would be great to share ,if you have, an example design circuit for ADC clock.

Thanks,

Anıl Karabeyli

25.03.2014

  • 0
    TI__Genius 9695 points

    Hi Anil,

    I will recommend the 250MHz clock input so you can bypass the internal divider since synchronization is your main concern. You can refer to the thread below for a discussion on this:

    http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/320706.aspx

    However, if some components on your system require 500MHz or 1GHz, then it is advisable to provide this frequency as the input to the ADC and use the internal divider.  This will help reduce the harmonics in your system. The ADC performance will be the same, regardless of the clocking option.

    The design package has an example drive circuit for the ADC clock on sheet 1 of schematic. You can download from here

    http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slrr004&fileType=zip

    Thanks,

    Eben.