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Minimum SPI Clock Rate for DACxx4S085 series?

Brian Henning1
Prodigy 10 points
Other Parts Discussed in Thread: DAC124S085, DAC084S085

Hi,

I'm in the midst of prototyping a four-channel digital voltage-controlled current-source, and I'm using the DACxx4S085 family of DACs to provide the control voltage.  At present I'm prototyping with the 8-bit version, DAC084S085, but plan to swap in a 12-bit DAC124S085 later.

The microprocessor platform which will send data to the DACxx4S085 is not through being designed, so I've been trying other ways to send SPI signals to the DAC.  So far, I have tried using an Arduino Uno I had handy, but the results are highly erratic.

I don't fully understand the SCLK and SYNC timing characteristics listed in the data sheet.  Does the "33ns" "minimum" mean that the SPI input can't be clocked any slower than 30MHz?  The Arduino can't clock anywhere near that fast, so if that's the case I'll have to use another MCU for my testing.

The wording in the datasheet is unclear.  If 25 ns is "typical," how is 33 ns "minimum" (it seems like "minimum" and "maximum" are used with opposite meaning...)

From the datasheet:

Symbol Parameter Conductions Typical Limits

Units
(Limits)
fSCLK SCLK Frequency 40 30 MHz (max)
1/fSCLK SCLK Cycle Time 25 33 ns (min)

Thanks for clearing this up.

  • 0
    TI__Genius 16890 points

    Hi,

    The fSCLK spec is a maximum meaning that the fastest the clock can be is 30MHz.  This is what is guaranteed, although parts will typically run up to 40MHz.  It will also work with a slower clock.

    Since the 1/fSCLK is the inverse of the fSCLK spec, it is specified as a minimum.  The clock cycle time is guaranteed to work down to 33ns (the inverse of 30MHz) but parts typically will work at 25ns (which is the inverse of the typical  40MHz clock frequency).

    Mike