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ADS6224 LVDS output

Calum Mackinnon
Genius 4155 points
Other Parts Discussed in Thread: ADS6224

Hey,

One concern I have with this ADC is the fact that the datasheet specifies it has LVDS compatible I/O’s but the LVDS buffer supply is specified as 3.3v. Usually LVDS is specified at 2.5v. If I am driving true LVDS inputs on the FPGA do I have a concern with voltage level mismatch? I assume this is taken care of in the part but could you check?

There are no max voltages defined for teh L\VDS outputs only typicals.

Cheers

calum

  • 0
    TI__Genius 17320 points

    Hi Calum,

    The LVDS standard does not specify the buffer supply voltage. You'll find LVDS devices with supplies from 2.5 V to 3.3 V. The ADS6224 does meet the LVDS standards (1.2-V Vcm, 250 to 450 mV swing). There probably should be a min/max for either the common-mode voltage or the high/low level outputs. However, if you look at an FPGA datasheet, the input common-mode voltage range is typically from less than 0.5 V to greater than 1.8 V. This is a large range that will greatly exceed any PVT variation in the ADC's output common-mode voltage.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Genius 4155 points

    In the ADS622x datasheet, I see referenced DCx, DDx on pgs. 54 – 58 but this part only has 2 sets of LVDS outputs. Pg. 59 on describes DAx and DBx. Is this a cut and paste error from a 4 output device?

    Cheers

    Calum

  • 0 in reply to Calum Mackinnon
    TI__Genius 17320 points

    Hi Calum,

    Yes, this is a copy and paste error from the quad version of the device (ADS624x).

    Regards,
    Matt Guibord