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Issues in interfacing ADS54RF63EVM and DAC34SH84EVM with Xilinx ML605

Other Parts Discussed in Thread: ADS54RF63EVM, DAC34SH84, CDCE62005

Hi,

 I went on to interface the ADS54RF63EVM board and DAC34SH84EVM board with a Xilinx Virtex 6 ML605 board.

1. I am using the 19.2 MHz crystal source inside the DAC34SH84 to generate a 270 MHz clock for both the DAC board, and FPGA board. I am using this clock inside the FPGA to send to the ADC board, to use at it's clock. 
 -- Is there any problem with this ?

2. I am using a 3 Mhz, 1 V p-p sine wave to send to the ADS54RF63EVM board, and I expect a sine wave output at the oscilloscope at the DAC output. 
 -- But, what I observe is a waveform (non-sinusoidal, 22 MHz, 2.2 Vp-p)  which does NOT change with any change in the input frequency !
 -- This waveform remains even after I switch of the ADC input. Could you give me any help in suggesting why this could happen?
 -- Once I remove the ADC clock (which is coming from FPGA), the waveform is not there. Does this mean that there is some sort of clock leakage ?


Thanks a lot in advance,
Basil

  • H

    1)  If you are using a clock from an FPGA to source a clock to a high speed ADC, then you will not get anywhere near the datasheet performance from the ADC.  A clock generated from an FPGA will just have too much jitter on the clock to get good SNR performance from a high speed ADC.   It should be functional, but with not as good an SNR performance as you would get compared to having a good quality low-jitter clock source for the ADC. 

    2)  You must have some problem with your FPGA coding.  I cannot help you with that.  I would suggest looking at your signal path in steps and seeing if you have the right signals at each step.   You could use a known-good capture tool such as the TSW1405 to capture the samples from the ADC to see if the setup is good through the  ADC EVM.  Or you could use a logic analyzer to capture the digital signals before adn after the FPGA to see if you have the expected data.  Inside the FPGA, you could use the chip-scope feature in the Xilinx tools to check the data path at varous points along the way.

    Regards,

    Richard P.

  • Thank you Richard for the reply.

    1. Okay, I will get myself a good quality clock source instead of the clock from the FPGA. 

    2. I used chip-scope to observe the signals inside. Please correct me if I am wrong. My understanding is that, the data coming into the FPGA from the ADC should change at every transition (both rising and falling) of the DRY signal. But, this is not what I observe!

    3. Does the ADS54RD63EVM introduce any sort of loading ? I am asking this because, I gave a 600 mVp-p 250 Mhz signal to the clock input, and when I observed it at the pin (via a probe to the oscilloscope), the voltage had dropped to 80 mVp-p. Is this because of the ADC board loading the clock input (or) because of the probe (or) because of the clock source not being a good driver? 

    Thanks a lot, and apologies for multiple posting. 

    Regards,

    Basil.

     -- 

  • Hi,

    The sample data bits and the DRY clock siignal *do* transition at the same time, as illustrated in Figure 1 of the datasheet.  If you look at these signals with a couple channels of a scope at the pins of the ADC you should see them transition togehter to within some tolerance.  But if you use chipscope to look at the clock and data inside the FPGA *after* the IDELAY cells and after buffering in the FPGA then you will likely see something else.

    the clock input is relatively high impedance as seen in Figure 57 of the datasheet with about a 1Kohm biasng to the desired common mode voltage.  So no, not much loading.   But external to the ADC on the EVM is a termination resistor to terminate the 50 ohm coax that is usually used to bring a clock signal into the EVM.  If you are using a single-ended CMOS output from the FPGA for the clock source then these FPGA outputs are not made to drive a 50 ohm load and the signal will be loaded down significantly.

    Regards,

    Richard P.

  • Hi Richard, 

     Thank you for the detailed inputs.

     I also would like to get to know about the register settings for DAC34SH84EVM. The user guide provided, hardly has any detailed description for the same. Is there any way I could get any documentation for the same? Also, should I put up a separate post for this query ?

    Thanks a lot once again, 

    Basil.

  • Hi Basil,

    The EVM User's guide has reference to some example register files in the default GUI folder:

    C:\Program Files (x86)\Texas Instruments\DAC348x\EVM Configuration File Released\DAC34SH84

    The example contains 4x interpolation, NCO and QMC circuits enabled. You may refer to the guide section 2 also for a brief description of each digital blocks. For detailed description, please refer to the datasheet and the following app note:

    http://www.ti.com/lit/pdf/slaa584

    Some examples of the CDCE62005 Synthesizer mode with the DAC348x family are also in the same register file folder. You may need to adjust with the proper divider settings to yield 270MHz output. The clocks forum will be able to help you make the proper adjustments to the CDCE62005.

    -Kang

  • Hi Kang,

     Thanks a lot for pointing out the example register files. I am trying to understand what each of those are, with reference to the DAC34SH84 datasheet.

     In order to generate my 270 MHz clock signal, will the loop filter settings in the CDCE62005 also matter? If yes, how should I tune them?

    Thanks,
    Basil.

  • Hi,

    the loop filter will impact the shape of the phase noise. The clocking forum support can help you further on the CDCE62005 configuration.

    -Kang