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How can i guarantee a Global Power Down status of the ads62PXX (i.e. ads62p48) after power up?

Other Parts Discussed in Thread: ADS62P48

Briefly, my question is, when the ADC's reset pin is connected to a controlling pin of another chip ( NOT hare wired to ground, and this controlling chip and the ADC are powered up at the same time. So the LOW on reset pin can be achieved a short delay after power up.) and the parallel control pin ctrl1/ctrl2/ctrl3 are hare wired to 100b, will the ADC be in the Global power down mode after power up?

Here are more details.
In my design, the ads62p48 control pins trl1/ctrl2/ctrl3 are hard wired to 100b and SEN,RESET,SDATA,SCLK are controlled by an FPGA. The data input interface of the FPGA is configured as LVDS.

I want the ADC to be in Power Down mode after power up, that is, a high impedance status of the digital output, before it is configured through the serial interface to LVDS output.  As I think it undesirable for the ADC cmos outputs to drive the FPGA lvds inputs, I want the ADC to startup in Global power down mode with outputs in high-Z state.

I need configure the ADC using serial interface, so its reset pin is connected to an FPGA, not hard wired to ground. ADC and FPGA are powered up at the same time. So, a LOW on the reset pin can NOT be guaranteed before & during power up.

The paragraph 'USING BOTH SERIAL INTERFACE AND PARALLEL CONTROLS' in Datasheet ads62p48.pdf (the latest version from TI) describes what I care, but not clearly. It says, ... For increased flexibility, a combination of serial interface registers and parallel pin controls (CTRL1 to CTRL3)
can also be used to configure the device. To allow this, keep RESET low. The parallel interface control pins
CTRL1 to CTRL3 are available. After power-up, the device is automatically configured as per the voltage settings
on these pins (see Table 6)... 

LOOK! Here, 'table 6' describes pin SEN, NOT ctrl1/2/3 ! Here, I GUESS, should be Table 7.

Does the above paragraph mean that the 3 and only the 3 control pins ctrl1/ctrl2/ctrl3 will decide the power up status of the ADC i.e. Global power down ?
Reset pin does NOT participate in this decision, and neither do the internal registers. For the datasheet does not offer default values for these registers.

The words 'To allow this, keep RESET low.' in this paragraph is puzzling. '(see Table 6)' puzzles again.
And there are 2 parts in the datasheet describing register 40 about Power down modes inconsistently. On P22, D3-D0 <POWER DOWN MODES> 0000 Pins CTRL1, CTRL2, and CTRL3 determine power down modes.
1000 Normal operation. But on P65, Normal operation <POWER DOWN MODES> = 0000  ...   P22 seems correct.

Alan Ku

  • Hi Alan,

    When using both parallel and serial modes, I believe RESET can just be tied low altogether. Upon start up the state is determined by the CTRL pins. You can then issue a software reset using the SPI interface and program the part as appropriate, including taking it out of power down mode.

    Matt Guibord