JDSU asked about the abs max table on the ADS58B19.
The Absolute Maximum Ratings table says RESET, SCLK, SDATA, SEN can have a maximum of AVDD + 0.3 and AVDD is 1.8V which would be 2.1V max. However in the Digital Characteristics table (on page 6 of the datasheet) it says these signals support 3.3V CMOS logic levels which seems to contradict the Absolute Maximum Rating. JDSU would like to drive these signal with 3.3V CMOS. Which table is correct?
I am wondering if the Abs max should actually be referenced to AVDD_BUF+0.3 instead of AVDD+0.3? I ask because I see that we had an error in the ADS41B29 (from this E2E post). If so, is it all inputs including RESET, SCLK, SDATA, SEN.
http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/155044.aspx
We need an answer to this ASAP since they did their schematic and layout with 3.3V logic, and need to know if they have to stop boards being built to make the change.
Thank you,
Mike Score
