In order to remove the influence by 500-MHz noise interference,
1k ohms resistances were inserted in the serial signal lines sync , sclk and a din terminal in series.
Does this usage suit?
I do not want to change a PCB layout as a premise.
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In order to remove the influence by 500-MHz noise interference,
1k ohms resistances were inserted in the serial signal lines sync , sclk and a din terminal in series.
Does this usage suit?
I do not want to change a PCB layout as a premise.
Hello Yoshida-san,
This method should work. The 1kΩ resistor should interact with the small parasitic capacitance on the pins and give you a cutoff to eliminate this noise at >100MHz. I have never tested it in the lab myself, but I have seen many customers do it with different devices without any issues.
I will try to find out if we have any previous characterization measurements on the digital pins parasitic capacitance, but the total effective capacitance will also depend on the layout. Mostly the sizes of the traces that connect to the pin.
Hi Eugenio Mejia,
Your opinion was consulted very much.
The cut-off frequency was estimated as follows.
31MHz = 1/(2pi*1kohms*5pF)
※5pF=3pF(Pin capacitance max) + 2pF(Parasitic capacitance was estimated roughly.)
I am going to evaluate and check how much margins there are.
Thank you.