Please let me know below about the output timing of DAC3152.
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The following is written on the 7&14th page of the datasheet.
・Ach is a rising edge of DACCLKP.
・Bch is a falling edge of DACCLKP.
・Latency is typ 1.5 cycle. (Input=>Output)
In this case, the timing of output:(1) or (2),which is right?
(1):The output is update simultaneously about IOUTA/B.
(2):The output side is update individually about IOUTA/B.
※The image figure should look at attachment.
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Best regards,
Satoshi
