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DAC TLC7524 as BDAC

Jaakko Nevala
Prodigy 20 points
Other Parts Discussed in Thread: TLC7524, DAC8541

Hello, I have designed a circuit using TLC7524 in BDAC (voltage) mode. I have run some test results already with a test bench circuit and the results were promising.

How ever I would like your opinion of my design if I may.

I am using 5V (buffered) reference and 10V (buffered) supply voltage. After the buffer amp I am getting 0.293V - 5V output, which is fine for me. Sorry about the messy schematic view.

I chose this model and mode, because I don't want to play with negative voltages and I have +3.3V 8 bit input, which is used without CS/WR. Original idea was to use 20V reference voltage, but I figured out that the supply voltage needs to be higher than the reference voltage and higher reference voltages would require higher input voltages. This may be obvious to you, but it should have been said in the datasheet.

So what do you think of this?

  • TI__Genius 10615 points

    Hello Jaakko,

     

    Jaakko Nevala said:
    I have +3.3V 8 bit input, which is used without CS/WR

    The DAC VIHMIN should be close to the VDD voltage. Somewhere around +8V. Take a look at page 3 in the datasheet. You said that this setup is working in a bench?

    Jaakko Nevala said:
    Original idea was to use 20V reference voltage, but I figured out that the supply voltage needs to be higher than the reference voltage and higher reference voltages would require higher input voltages. This may be obvious to you, but it should have been said in the datasheet.

    I understand that this is not obvious. The comment should definitely be in the datasheet. If the datasheet is updated again this will be in the change log, thank you for the report.

     

    Just to give you some options, take a look at the circuit below. It should behave the same as your current circuit, but with improved linearity since both Iout terminals are at the same potential. This keeps both switches inside of the DAC biased at the same potential, even though there is still the limitation of having VDD be larger than the Bias voltage.

     

    Are you planning on gaining the circuit to +20V?

    Is the parallel interface necessary for speed?

    The TLC7524 is a pretty old device. I could suggest a few other devices if you can share some details of the system application and goal.

  • in reply to Eugenio Mejia
    Prodigy 20 points

    Thank you for the answer Eugenio.

    Eugenio Nejia said:

    The DAC VIHMIN should be close to the VDD voltage. Somewhere around +8V. Take a look at page 3 in the datasheet. You said that this setup is working in a bench?



    Yes I know that, but I made a test configuration and tried to see how much I can push the VDD up with 3.3V VIH. Device still identifies 3.3V as HIGH with 10V VDD and 5V Vref. If I use lower VDD/Vref the output linearity suffers even more.

    Eugenio Nejia said:

    Just to give you some options, take a look at the circuit below. It should behave the same as your current circuit, but with improved linearity since both Iout terminals are at the same potential. This keeps both switches inside of the DAC biased at the same potential, even though there is still the limitation of having VDD be larger than the Bias voltage.

    Thanks, this looks promising, but again if you think that the VIHMIN should be around 8V then I might have a problem.

    Eugenio Nejia said:
    Are you planning on gaining the circuit to +20V?

    Yes with another Operational amplifier.

    Eugenio Nejia said:
    Is the parallel interface necessary for speed?

    Not for speed, but the data is not coded as I tried to explain.

    Eugenio Nejia said:

    The TLC7524 is a pretty old device. I could suggest a few other devices if you can share some details of the system application and goal.

    I have already several of these available and time is of the essence. Target is to have precise 10V - 30V output with 3.3V datainputs. DAC output is first buffered, amplified and then it is connected to a non-inverting summer amplifier with a 10V so the final output voltage is 10-30V. The speed is not the top priority, but it doesn't hurt either.

  • in reply to Jaakko Nevala
    TI__Genius 10615 points

    Hello Jaakko,

    Jaakko Nevala said:
    Device still identifies 3.3V as HIGH with 10V VDD and 5V Vref.

    Unfortunately Texas Instruments cannot guarantee the performance of the DAC if the datasheet specifications are not met. The output performance should not be affected by using your scheme, but you run the risk of the DAC not reading the input values, or reading incorrect values.

    Jaakko Nevala said:
    If I use lower VDD/Vref the output linearity suffers even more.

    Linearity should not be affected by the level or ratio of VDD and Vref. How are you measuring a degradation in linearity?

    Jaakko Nevala said:
    I have already several of these available and time is of the essence. Target is to have precise 10V - 30V output with 3.3V datainputs. DAC output is first buffered, amplified and then it is connected to a non-inverting summer amplifier with a 10V so the final output voltage is 10-30V. The speed is not the top priority, but it doesn't hurt either.

    I understand that time is of essence but I highly advise against using the TLC7524 with 3.3V digital inputs as it poses a reliability issue.

    I suggest taking a look at the DAC8541. This DAC is a 16-bit voltage output parallel input DAC. you can still use it as an 8-bit DAC. This device has a separate DVDD pin to set the level of the digital inputs, which will accommodate for your 3.3V inputs. The package is a 32-pin TQFP package that has a lot of features that you most likely will not use in your application which may complicate your board layout.