Ads1672 datasheet is missing min and max values for tCLKDR

ArthurDent

Other Parts Discussed in Thread: ADS1672, ADS1675

Can anyone tell me the min and max values of tCLKDR (i.e. the CLK to DRDY delay)? The datasheet only list the typical value.

I will synchronize ten ADS1672. To reduce the number of interface lines I want to use SCLK and DRDY only from one of the ADCs. However, this is only possible if the DRDY (and SCLK) variations between the ADCs are not to large.

To make sure this will work I need the min and max values of tCLKDR.

Vidar

over 11 years ago

0 Greg Hupp over 11 years ago

TI__Mastermind 23235 points

Hi Vidar -

We can try and give you some better guidance, but we cannot provide min and max values since min and max values are guaranteed. Without testing many units across multiple conditions, we cannot guarantee these values.

Allow us some time to investigate and see if we can provide some better guidance.

0 ArthurDent over 10 years ago in reply to Greg Hupp

Prodigy 60 points

Hi Greg

That would be great.

I have had a look at the datasheet for ADS1675, which specify min and max for tCLKDR: 23 to 30 ns, i.e. a window of 7 ns. Is 7ns what I can expect on the ADS1672 as well?

In the datasheet for ADS1672:
In Figure 1, tCLKDR is measured from the negative edge of CLK, while in Figure 2 tCLKDR is measured from the positive edge of CLK. Is this correct?

BR
Vidar

0 Greg Hupp over 10 years ago in reply to ArthurDent

TI__Mastermind 23235 points

Hi Vidar -

Give us some time to confer with the design team to see what we can share. I will keep you updated.

0 Greg Hupp over 10 years ago in reply to ArthurDent

TI__Mastermind 23235 points

Hi Vidar -

We wanted to provide you with a quick update.

We are continuing to collect information, but in regards to the comparison of tCLKDR between ADS1672 and ADS1675, this is a good guideline. While we can't guarantee the values for the ADS1675, using the ADS1672 plus a little margin should be a good first order estimate.

0 Kevin Shaw41 over 9 years ago

Prodigy 30 points

Hi Vidar,

Did you end up using SCLK and DRDY from only one ADS1672? If so, how did it work for you?

Thanks,

Kevin

0 ArthurDent over 9 years ago in reply to Kevin Shaw41

Prodigy 60 points

No, I did not use SCLK and DRDY from only one ADC.
My ADCs are isolated from the digital interface, and the max/min delay variations of the isolators together with the max/min values of the ADCs digital interface were too large for this to work.

Vidar

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Ads1672 datasheet is missing min and max values for tCLKDR