ADS7223 register access

I am working with the ADS7223 ADC.

Regarding the configuration interface (in specific access to the REFDAC registers) I could not fully keep my interpretation of the data sheet - and the way I have seen the chip to operate in sync.

-------------------------- according to the data-sheet
RD (read data) and CONVST can be shorted to minimize the necessary
software and wiring. ...
Therefore the combined signal must be activated with the rising CLOCK
edge.

The contents of these 16-bot registers can be set using the serial data
input (SDI), ... and clocked into the device on each falling edge of CLOCK ...

and as depicted in Figure 40:
CONVST and RD are active for one half clock period (CLOCK positive edge to
negative edge)
First bit of SDI is sampled by the device on first negative edge after CONVST being high -
hence simultaneously to CONVST/RD going low.

-------------------------- observed behaviour
This seems to be not the case with my setup (refer attached picture for a logic trace of the interface signals).
The data is shifted by 1 bit, Hence the first bit on SDI is sampled on the second negative edge - after CONVST
becoming high (on a positive edge).
My setup puts CONVST/RD to low with a negative edge of the CLOCK. In contrast to the data-sheet figure the device does not sample SDI on this negative edge.

This implies CONVST/RD to become low on a negative edge - and the next negative edge marks the first data bit.

If this is the intended behaviour I would have some questions related to the required setup/hold times of CONVST/RD with respect to the CLOCK.

My other interpretation is a little inaccuracy in the data sheet.
If CONVST/RD should be high for a full clock period (hence from positive to positive edge), the description of SDI would be correct (sampled at first negative edge after CONVST becoming low).