ADS5282 EVM to Zedboard (Xilinx Zynq) reference design

Hi,

Our TSW1400 capture card is based around an Altera FPGA and the TSW1405 capture card is based around a Lattice FPGA.  The older TSW1200 capture card was based around a Xilinx FPGA, which was Virtex4 at the time.  (We wouldn't have code specifically for th Zynq.)  The Xilinx has cells that make it easy to interface to the DDR LVDS data from the ADC, particularly the IDDR cell that latches the data on the rising and falling edges of the DDR clock and the IDELAY cell that can be adjusted to meet setup adn hold time into the IDDR cell.  Please see the attached sketch of how the interface from the ADS5282 was done in the TSW1200 Virtex4.   You would have to use the static timing analysis tools from your FPGA development tools to determine the IDELAY tap settings that would close timing for your interface into the Zynq.

After latching the data from the ADC, there remains the job of deserializing the data from one LVDS signal down to the parallel bus of 12 bits.  The sketch also shows how I chose to do that in the TSW1200, making a shift-register chain of flipflops and using the Frame Clock (sometimes called ADCLK) to know when to move the data from the shift register into the parallel register.  After the data is converted back into 12bit samples, you are free to do what you will with it in your FPGA.

Regards,

Richard P.