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LM97593 input RF from 21.400MHz to 55.000MHz

Neeraj Gill
Mastermind 20541 points
Other Parts Discussed in Thread: LM97593

HI Team,

Here my orignal question about LM97593.

 I am using LM97593. I wants to know, are there any pitfalls with the device’s internal SFDR that would drive a change in the NCO frequency, and/or the CIC and FIR filter configuration? If he change the design from

Currently:

  • Input RF is 21.400 MHz
  • Information bandwith is 16kHz
  • ADC clock rate is 22.050 MHz (requires decimation)
  • Internal NCO frequency is 650kHz
  • CIC and FIR filters are programmed to support decimation and our specific sensitivity requirements with the above hardware configuration. Settings for these filters were arrived at through consultation with the known National factory support engineer at the time (ca. 2008-2009), plus some trial and error optimization on our part.

 

  To

Design Change – we are looking doing the following

  • Input RF is 55.000 MHz
  • Same information           bandwidth
  • ADC clock rate = 55.65           MHz. But could also be 54.35 MHz (VERIFY)
  • Internal NCO frequency           is 650kHz
  • CIC and FIR filter           programming – TBD (based on consultation)

 He also wants to know if he would be better off using the low-side clocking of the ADC instead of high-side clocking.( He is currently using high-side clocking of the ADC.)

 

Below is the response I recieved for post

In jumping up to a higher sampling rate, but maintaining an IF 650kHz away from the sampling rate causes the aliased IF to be closer to DC (as a proportion of Fs) compared to the original situation. This can cause the original settings for the decimation filter to be inadequate for the new settings.

For instance, when Fs= 22.05MSPS and Fin = 21.4MHz, then IF frequency = 0.65/22.05 = 0.029*Fs and the BW=0.016/22.05=0.00073*Fs. In this case, one would design the NCO freq to be 0.029*Fs and the decimation filters to cut off at ~0.0010*Fs. After you change to Fs=55.65MHz, the IF frequency = 0.65/55.65 = 0.012*Fs and the BW is 0.016/55.65=0.00029*Fs which indicates that you should change both the NCO and the filters because the IF has proportionally shifted.

As for the SFDR performance, the HD2 and HD3 and IMD2 of the signal chain and ADC should all fall out of band and be digitally filtered out. IMD3 of the ADC (as well as the signal chain) will worsen slightly because you are running at a higher IF frequency (and higher sampling rate) with the same hardware. I would estimate that the IMD3 of the ADC would degrade ~3 dB relative to the carriers at the higher IF.

Whether one does low-side or high-side clocking is insignificant in this case because the IF is so close to the sampling rate. Chooing one or the other may make it more convenient to keep track of phase polarities in the digital domain because sampling in the 3rd Nyquist zone causes a phase inversion compared to the 2nd zone. There may be some 2nd order effects related to having a different sampling rate which may be significant, but you would need to try that in your system to really know if one is better than the other.

Regards,

Neeraj Gill

  • 0
    Prodigy 60 points

    The question posted above was done on my behalf. I am the TI customer who is attempting to make the changes described. They were forwarded from my local TI rep. Based on the observations and advice about keeping the same relative IF freq/Fsampling ratio, I made an attempt to derive the new NCO and decimation filter settings. Please review this and let me know if I am correct.

    Our Current Architecture:

    • Input RF is 21.400 MHz
    • Channel bandwidth, BW, is 25kHz (treat this as the desired information bandwidth)
    • Sampling frequency, Fs is 22.050 MHz (requires decimation)
    • FIF = 22.050 MHz – 21.400 MHz = 650kHz
    • FIF = 0.650/22.050 = 0.029478∙Fs
    • BW = 0.025/22.050 = 0.001134∙Fs

    New Architecture

    • Input RF is 55.000 MHz
    • Want to retain the same FIF/Fs ratio
    • Keep high-side sampling (e.g. Fs > FRF ), thus new Fs = FRF + new FIF
    • Derive:                                 FIF = 0.029478∙Fs = 0.029478∙(FRF + FIF)

    Solve for FIF :      0.97052∙FIF = 1.62129 MHz → FIF = 1.67054 MHz

    • New Fs = 55.000 MHz + 1.67054 MHz = 56.67054 MHz

    Not precisely sure how to handle change in the decimation filter settings. The original settings (unknown until I figure out the code) handled a 25kHz channel bandwidth with a sample frequency of 22.050 MHz → BW = 0.025/22.050 = 0.001134∙Fs

    Does the decimation filter bandwidth get increased proportionally, e.g.

    0.001134∙Fs = 0.001134∙56.67054MHz = 64.252kHz ??

    -Thomas Shafer

  • 0 in reply to Thomas Shafer
    TI__Expert 4340 points

    Thomas,

    If you change the frequency of the CLK input, the sampling rate of the ADC changes, but the processing rate of the back-end also changes proportionally. For a given NCO and decimation and filter design, the resulting filter properties will maintain the same relationship to Fs for all CLK frequencies. For instance, if the lowpass filter cutoff frequency used to be 0.04*Fs, then it will remain 0.04*Fs after the CLK frequency change.

    Your calculation for the new sampling rate looks good. You are keeping the IF frequency the same proportion relative to the sampling rate, so your existing NCO, decimation and filter design settings can still all apply to your design. The result is that the unfiltered BW and the output data rate have increased proportional to the increase in the sampling rate. You must consider the impact that this has on your receiver performance and the ability for your processor to receive the data at the increased rate. If this is OK, then you're done.

    If the increased BW and data rate is not OK, then you need to adjust your decimation and filter settings. If that is required then we must dive deeper to accomplish that.

    Regards, Josh

  • 0 in reply to Joshua Carnes
    Prodigy 60 points

    Josh,

    Thank-you for your response. Is there a document to which you can provide a link, or send me, that explains what goes on in the digital filtering that will help me understand your response? I am glad to know that I chose the correct Fs. But I'd like to understand things better since I expect that when we start prototyping, adjustments will have to be made.

    Thomas Shafer

  • 0 in reply to Thomas Shafer
    TI__Genius 12965 points

    Thomas,

    Digital signal processing is a topic that is out of the scope of this forum - however I have included below a few wiki links which help explain discrete time signals, digital signal processing and digital filtering.  There should be quite a few links within these wikis to help you understand the concepts.

    http://www.dspguide.com/pdfbook.htm

    http://en.wikipedia.org/wiki/Discrete-time_signal

    http://en.wikipedia.org/wiki/Digital_signal_processing

    http://en.wikipedia.org/wiki/Digital_filter

    Also a google search of disrete time sampling will yield many hits that can help with these concepts.

    Ken.

  • 0 in reply to Ken C
    Prodigy 60 points

    Ken et al,
    Thank-you all for your responses. I do have some experience with subject matter in this thread, but definately below the day-to-day familiarity you all have. I am basically trying to pick up where another engineer left off with our existing design. As you can tell from the earlier exchange, I'm examining a redesign of the DDC frequency planning and want to ensure I've accounted for all potential pitfalls.
    Can someone help me understand the operation of the LM97593 with regards to our current setup, and confirm my understanding of how to modify it for the new frequency plan? Please continue reading below...

    Current Architecture
    • Input RF is 21.400 MHz
    • Channel bandwidth, BW, is 25kHz (the information bandwidth is ~16kHz)
    • Fs is 22.050 MHz (requires decimation)
    • Fif = 22.050 MHz – 21.400 MHz = 650kHz
    • Fif = 0.650/22.050 = 0.029478∙Fs
    • BW = 0.025/22.050 = 0.001134∙Fs
    This puts the sub-sampled signal in the second Nyquist zone (between Fs /2 and Fs). I understand that because of this there is fold-over resulting in a flipped spectrum.

    As I understand the operation of the DDC portion of the LM97593, the down-conversion is done before any decimation. Correct?
    Our current programming of the LM97593 is:
    • we only use Channel A
    • value of Reg 0 = 0x4a (So N=74, and decimation factor is 75 in the CIC filter)
    • value of Reg 1 = 0x00 (So decimation factor is FIR2 is 2. Does this mean total decimation is equal to 150??)
    • values of Reg 7-10 are 0x75, 0xE6, 0x8B, and 0x07 respectively (so FREQ_A = 0x78BE675, and the NCO frequency = ([0x78BE675]/2^32)*22.050E6 = 650kHz

    I am confused about what is the final data rate after decimation.
    1. Start with Fs=22.050MHz
    2. Down-Convert using quadrature NCO to 650kHz. Sample rate is still 22.05MHz? Yes?
    3. Decimate by 75 in CIC and again by 2 in FIR2, for a total of 150?

    22.05MHz/75=294kHz, and 22.05MHz/150=147kHz. These two values are meaningless to me.
    However, 650kHz/75=8.667kHz. This means something to me, as it is half of the information rate (see above).
    But 650kHz/150 would be too small a number. So I am also confused about the decimation factor in FIR2.

    Can you explain to me the mechanics of what is actually happening? I believe I am missing something about what is the true sampling rate of the IF signal before and after downconversion using the NCO, and before and after decimation in the CIC, FIR2.

    Thanks all for your continued interest in helping me.

  • 0 in reply to Thomas Shafer
    TI__Expert 4340 points

    Thomas,

    From your description, it appears that the signal is being sampled in the 2nd Nyquist zone, 650kHz offset from the sampling rate, therefore the channel aliases down to 650kHz in the sampled spectrum. From there, the NCO mixes the channel by 650kHz down to complex baseband (complex digital representation centered at DC) and then decimates/filters the spectrum.

    Yes, it appears that the CIC decimates by 75x and FIR by 2x for a total decimation of 50x, bringing the data rate from 22.050MHz down to 147kHz. Note that this is the data rate of data transferred from the LM97593 to the next signal processing block and is not the data rate of the signal contained in the 25kHz channel.

    I'm not sure about the 650/75=8.667kHz value that you recognize. 

    Regards, Josh