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DAC3171EVM connection to Altera Development Kit via HSMC connections

Other Parts Discussed in Thread: DAC3171EVM


I want to evaluate the DAC3171EVM using my Altera Stratix IV GX FPGA Development Kit via HSMC connections.

On the TI site it is written that one of the DAC3171EVM features is:

"Direct HSMC connection to Altera FPGA development kits", however I checked the HSMC schematics connections on both boards (DAC3171EVM and Altera Stratix IV GX FPGA Development Kit) 

It seems that there is a HSMC connection conflict - for example: On the DAC3171EVM J14A Pin 9 is connected to ground and on the Altera EVB this pin is connected to Tx output (J2 pin 9).

I am concerned that I might damage my Altera board if I connect it directly to the EVM3171EVM via the HSMC connector.

Could someone please advice if I can use my Altera Stratix IV GX FPGA Development board in order to evaluate the DAC3171EVM ?



  • Hi,

    i would suggest you contact Altera directly about that particular conflict and any others that you might find, just to be sure.

    I would expect that since you will be programming the FPGA for the application that you have under development, then you would just *not* program the FPGA to actively drive that signal.  Generally FPGAs don't enable their IO pins to be output drivers until the bit file is loaded into the FPGA and then the bit file tells whether the IO is to be an output or not.  So I would not expect there to be a problem.  But I do not have direct knowledge of that development platform.

    I surveyed a number of our DAC EVMs that support LVDS signaling on that particular connector and some of them have pin 9 grounded and some do not.   I do know that back when we were developing the bridge cards to bridge our ADC EVMs and DAC EVMs to the popular FPGA development platforms, we had someone from the FPGA vendor advise on the pinout into the development platform.  That is, for the bridge card for our ADC EVMs into the Altera development platform we had an Altera person choose the pins of their connector that our bridge card would route to.  But for our DAC EVMs with LVDS sample bus, our EVM already happened to use a connector that mated up to the Altera development platform so no bridge card was developed.   And the pinout of our DAC EVMs was already deemed acceptable for the pin assignment of the FPGA develpment platforms.    And all of our DAC EVMs with LVDS signalling put the clock and data pairs on a common set of pins that do work well with the FPGA development platforms.  It's the other minor variations from one EVM family to another such as ground on pin 9 that I cannot directly speak to and so I would have to defer to the FPGA vendor.

    Richard P.