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DAC5652A WRTIQ and CLKIQ setup/hold

Hugo Van Dessel
Prodigy 20 points
Other Parts Discussed in Thread: DAC5652A

Where can I find the setup and hold relation between WRTIQ and CLKIQ on the DAC5652A used in interleaved mode?

I cannot find any timing info in the datasheet.

 

Best regards

Hugo 

Sr. FAE EBV

 

 

  • 0
    TI__Expert 7445 points

    Hi Hugo,

    as mentioned on parallel loop, I'll be checking directly with application guys in the product line, then back to you (or maybe they'll anyway answer here)

    Best regards

    Sergio

  • 0
    TI__Genius 9695 points

    Hi Hugo,

    No setup/hold times are defined for WRTIQ or CLKIQ because WRTIQ is not latched by CLKIQ or vice versa. Both these inputs are clocks and the correct timing relation to ensure reliable data transfer between these two clock domains is handled inside the DAC. The only constraint on these clocks is that their rising edge must occur at the same time or the rising edge of CLKIQ must occur before rising edge of WRTIQ. This timing relationship is described on pg 12 of datasheet under the dual bus interface mode but it should also apply for the single bus mode.

    Thanks,

    Eben.