ADS6425 internal reference setting

Hi,

The full scale input voltage is designed to be about 2 V peak to peak differntial.  The external reference mode of operation is designed to allow for a small range of adjustment of full scale, but not for large range of adjustment.  One such case where an application might call for external reference would be where more than one device is used and an external reference applied to all the devices would remove device-to-device variation in the full scale range.

The datasheet calls out two ways to enable external reference mode, either by control voltage on the pin SEN (page 11 of datasheet) or by setting a SPI register bit (bit 5 register A page 16).

The external refernce section on page 34 describes how the VCM pin becomes the external reference input and gives the equation relating the external reference voltage to full scale range.  An external reference of 1.5V is gained up internally to a voltage of 2V to set the full scale range to 2V.  The external reference range is limited to 1.45V to 1.55V.

Figure 25 shows the effect of small changes in reference on SNR and SFDR, and illustrates why the external reference is to be limited to the range of 1.45 to 1.55V.

For smaller input signals than 2V peak to peak differential, there are two options for internal gain of the signal. A fixed gain of 3.5dB can be applied and an adjustable gain of 0 to 6 dB can be applied.  Table 19 shows the effect of gain setting on the effective full scale range after gain.  The fixed course gain and adjustable fine gain may be both applied at the same time for total gain of up to 9.5 dB.

With or without gain and with internal or external reference the input signal must still be biased to a common mode voltage of 1.5V.

Regards,

Richard P.

Hi Richard,

I'm connecting the SEN pin to (5/8)LVDD using the 3 R's setting as on Figure 3, so it's suposed to be setting the ADC to work with the internal refference and 3.5dB coarse gain, right? As I understand the fine gain shoul be programmed using the serial interface and writting onto the appropiate registers, I guess I will be able to do so from the FPGA but, if the SEN pin is tight to that fixed voltage, is it enabling the serial interface at the same time?

I'm also setting the other Parallel Pins using the same "resistor network" tighting them to the different voltages depending on the setting I need, in this case:

PDN -> Tight to 0 (GND, right?) for a normal operation.

CFG1 -> I'm thinking to connect it to (5/6) LVDD or maybe LVDD depending if I'm gonna use the DDR or SDR Bit Clock.

CFG2 -> LVDD, but as I understand it depends if the but clock is set to be on SDR, what if it's set to DDR?

CFG3-> GND (as it says its reserved so it should be connected to GND)

CFG4 -> I've choosed the LSB and 2s complement connecting it to LVDD and I guess that this implies to program the FPGA accordingly to receive the data properly.

I'm connecting the serial communication pins to the FPGA so I can set the registers, so RESET, SCLK and SDATA pins are directly connected to the FPGA if that is correct, do this lines require any extra component?

Around the same matter, I'm placing a 100ohm resistor between all the LVDS line pairs from the ADC to the FPGA ( for all the outputs in 2 wire mode and frame and bit clock pairs), is that correct or do I need to place any other component and/or minding any other consideration?

Pheeew, I guess there I'm placing quite a lot of questions here! Thanks for your wisdom!