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Data sheet suggests 20 MSps ADC only useful for up to 100 kHz?

Oliver GIlmour1
Prodigy 20 points
Other Parts Discussed in Thread: AMC1305M25, AMC1304M25, ADS1118, ADS1248, TMS320F28377D, ADS5560, ADS1610, ADS5562, AMC1210

HI,

I'm interested in the AMC1305M25 ADC chip, I'm hoping to achieve 16bit resolution at 20 MSps data conversion using this chip with an MCU (not really dependant on the MCU, but I'm hoping to use a MCU if I can).

The analog signal I'm hoping to capture will have a highest frequency component around 400 KHz, so I wanted an ADC that can do faster than 10 MSps at 16 bits.

But looking at the spec sheet of AMC1304M25, all the characteristic curves which has input frequency for the x axis only goes up to 100 kHz.

This seems to me like a low cut off for something that is sampling at 20 MHz. Can anybody give me some clarity to my logic, or point out what am I missing here?

Thank you in advance.

Oliver

  • 0
    TI__Genius 9975 points

    Hello Oliver,

    Sorry for the delay in my reply.

    The AMC1304M25 and AMC1305M25 are isolated delta-sigma modulators. TI’s delta sigma modulators are indeed listed as 20 MSPS ADCs (and 10 MSPS in some cases) due to the framework in which the devices are classified. Technically speaking however, these devices are not to data-converters such as the ADS1248 or ADS1118, they are modulators.

    As shown in the Feature Description section of the AMC1305 datasheet, the output of the device is a stream of ones and zeros where the density of zeros is proportional to the ratio between the analog input signal and the internal voltage reference of the modulator. A more detailed description of the operation of delta-sigma modulators and data converters can be found at: http://www.ti.com/lit/an/slyt423/slyt423.pdf

    A digital filter is needed in order to produce a 16 bit codeword from a delta-sigma modulated bit-stream. You can find more information on the details about one type of digital filters commonly used (sinc filters) in: http://www.ti.com/lit/an/sbaa094/sbaa094.pdf

    The TMS320F28377D microcontroller has a digital filter module that readily takes a delta-sigma modulated bit-stream and filters it. More information on using the AMC1304 and AMC1305 in conjunction with the TMS320F28377D can be found at:

    http://www.ti.com/tool/TIDA-00171

    www.ti.com/tool/TIPD165

    If you do not need the galvanic isolation provided by the AMC130x devices and need 16-bits then you might want to explore ADCs such as the ADS1610 (a delta-sigma ADC) or ADS5560 and ADS5562 (pipeline ADCs).

    Hope this helps.

    Best regards,

    Jose

  • 0 in reply to Jose Duenas
    Prodigy 20 points

    Hi Jose,

    Thank you for clarifying this. The project I'm working on is now taking a slightly different direction so I won't be looking at the high speed ADC chips until January, but I will keep your advice in mind when I start looking at this closer.

    FYI, I'm not too bothered about galvanic protection, I'm trying to build a straight forward data acquisition board prototype. So for me having an ADC with 16bit resolution at 10 MSps is what I'm after, no size/power/interface/ADC type constraints just yet. Also my knowledge of ADC doesn't stretch that far so as far as I'm concerned, as long as I get my sample rate I'm not too bothered what ADC I go for, provided that my MCU can handle the interface.


    Thank you very much for your information. Big help indeed.


    Regards,


    Oliver

  • 0 in reply to Oliver GIlmour1
    TI__Genius 9975 points

    You are very welcomed Oliver! Glad the answer helped.

    Best,

    Jose

  • 0 in reply to Jose Duenas
    Prodigy 20 points
    Hi everyone,

    i hope I am in the right topic.
    For my student research project, I have to design/use a Delta-Sigma-Modulator with a low pass filter realized on an FPGA. Following conditions are given:
    Input Signal: 60 – 80 kHz (periodic)
    Resolution: 16 bit (min. 14 bit)
    Range: 0…100V

    I have to sum up the signal values during its period. When I get a Trigger signal, I know the period is over and I have to build the average of it.
    The aim is to detect very little differences between the periods . It is not so important when the differences exactly happen, just that they arrive in that period.
    Is it theoretically possible to reach this Resolution with the AMC1305M25? I got contradictory information about the possible resolution refering to OSR, SNR or SINAD. But there was no concrete formula to calculate with input values (range, frequency, bandwidth) the possible ENOB/ resolution.

    Many thanks for help!!

    Best regards,
    Phil
  • 0 in reply to Phil WB
    TI__Genius 9975 points

    Hello Phil,

    I suspect that it is impossible to obtain the 14 bit minimum resolution you seek with our delta-sigma modulator and a sinc filter. Here is why:

    You indicate that your input signal contains frequencies up to 80 kHz. There is no indication as to how many samples of the 80 kHz portion of the signal you would like to have (after all, you are averaging samples); however, your acquisition system will need to put out samples at a rate higher than 160 kSPS.

    Many of our modulators should be operated at 20 MHz (we do not have modulators recommended for higher clock frequencies). With this in mind, you will need a digital filter that decimates the incoming delta-sigma bit stream at no more than 125. For a sinc filter such as those in the AMC1210 and TMS320F28377D , we call that: OSR = 125.

    Figure 50 of the AMC1305 datasheet shows the expected typical ENOB for various filter types and OSRs. As you can see, for OSRs below 200, even a Sinc3 filter yields less than 14 bits.

    Admittedly, it might be possible to achieve 14 bits if you use a filter other than a sinc filter with decimation ratio of 125 or less; but you will need to characterize the modulator + filter combination in order to verify that.

    For a data rate higher than 160 kSPS and 16 bit resolution, my opinion is that SAR converters might be your best choice (and you will not need to implement a digital filter running at 20 MHz in the FPGA).

    Hope this helps.

    Best regards,

    Jose

  • 0 in reply to Jose Duenas
    Prodigy 20 points

    Hi Jose,

    thank you very much for your quick answer.

    Yes, it helped me determine more specifically how I would proceed. I will have a closer look at SAR converters.

    Best regards,

    Phil