Hi,
We are using ADS61JB46 moudle for AD conversion. Strange behaviour was observed when the module was implemented in the system. in the mid input power range, IF captured data look abnormal, seems like the data is damaged for whatever reason we don't know. in the upper region and lower region of power range, IF captured data look normal
input power range of -10 ~ 0 dBm => look normal
Input power range of -40 ~ -10 dBm => Look abnormal
Input power range of -50 ~ -40 dBm => Look normal, though not perfect
IF captured data are fed into FPGA for digital processing, and test was done with test pattern data provided by AD converter. test conditions are as follows.
- input to ADC: 76.9MHz(76.8MHz + 100kHz) singnal with varying power from -50 to 0dBm using E4438C signal generator.
- Clock: 61.44MHz clock signal to ADC and FPGA
- Output: 76.9MHz IF signal capture.
will appreciate so much if some can give us help tips on this issue.
Thanks.
