ADS62p48 Different Digital Output on Channels

Hi Juan,

I'm assuming this is on your own board and not on the EVM?

The ramp signal is likely telling you that your FPGA firmware is not quite right. I would not suspect a timing issue if the amplitude is always ~2x lower, so my guess is that you do not have the bit order correct. Can you please provide your captured data for the good and bad channel? I would like to see both the ramp and the I/Q input.

Regards,
Matt Guibord

Matt,

Thanks for getting back with me.

I'm attaching a file that has two different analog signal inputs one with QPSK data and the other with a Single Side Band (SSB). The digital outputs of these are also shown in the screen captures of I/Q digital output as well as the data. Test ramps are also included as well.

Additionally, there is an attached board schematic showing how the AD is wired up.

We are using a 100 MHz clock for the input and using an internal reference (reg 0x3f). We are also using -7/26 clock shift for the pos and neg edges.

Thanks again for your help.

Regards,

Juan

AD_DATA.zip

Hi Juan,

Looking at your ramp output, it looks like the Q channel is perfect, but the I channel has some errors. This looks like a timing issue since it's sporadic. You can see that the errors seem to fall into 3 states of deviation, meaning that it looks like you may have 3 bits not meeting timing. Taking a look at the actual numbers, you can see that the I channel ramp jumps by 1024, 2048, or 4096 codes. This indicates that there is a timing error on bits 10, 11, and 12 of the I channel. See the picture below to see the error.

I'm suspecting that you're using the LVDS interface. Check to make sure that you have enabled the 100 ohm termination in the FPGA. We've had a few times where this was not done and would cause similar errors. Otherwise, you'll need to review your timing constraints and verify that all bits are constrained correctly. If there is a difference in trace lengths, then you need to include these in your constraints.

You also have the bits inverted. This is obvious because the pattern is ramping down instead of up. This can easily be fixed in the FPGA although it may not effect your system at all.

Regards,
Matt Guibord

Matt,

Thanks for looking at this so quickly for us.  However, we are mostly concerned over the magnitude difference in Q over I.

ssb_iq.tifqpsk_sc.tif

Do you have any ideas why we are seeing this? We are really racking our heads over this. We do not have enough gain in the AD to balance these channels.

Please examine the QPSK data and see if you can see anything out of the ordinary.

If you can figure this out COB by Friday,  I'll owe you a beer or your preferred beverage of choice ;-).

Thanks again, looking forward to your reply.

Regards,

Juan

Matt,

We've confirmed the bit errors were in our logic analyzer connections.

Do you have any information about the gain mismatch we are seeing?

Regards,
Juan

Hi Juan,

Okay, now that you have the timing issues worked out can you run the test patterns again and send me your results?

And can you send me all of the register writes that you're doing?

Regards,
Matt Guibord

Matt,

Sorry didn't get back with you sooner, but we were trying something else out: the input clock frequency.

We changed the clock frequency to 200 MHz and found that the I/Q imbalance to be manageable now with independent gain controls. I hope this post helps someone in the future.

Thanks for your help.

Regards,
Juan