I wonder what is the model of Xilinx Programmer JTAG cable working with ADC08D1520RB to allow us to load new FPGA image on the board without causing conflict.
Thank yoU!
Best Regards,
-Bridget
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I wonder what is the model of Xilinx Programmer JTAG cable working with ADC08D1520RB to allow us to load new FPGA image on the board without causing conflict.
Thank yoU!
Best Regards,
-Bridget
Hi Bridget
If you are modifying the FPGA design, but still keeping it compatible with the Wavevision 5 infrastructure you can just name the newly created file the same as the one that is automatically loaded. Rename the original file first as a backup so you can return to the original design if needed. The file will be located in the following folder:
C:\Program Files (x86)\National Semiconductor\WaveVision5\hardware\fpga_images
The bit file for the board you have is named "adc10d1000_xc4vlx25_adc08d1520rb.bit".
If you do need to use a JTAG programmer, one like this should work: http://www.xilinx.com/products/boards-and-kits/hw-usb-g.html
Regards,
Jim B
Hi Jim,
-Bridget
/** Capture Parameters */
typedef struct {
/** UNUSED */
WvDouble DACFreq;
/** Size of capture in samples */
WvWord TransferSize;
/** Index to ChannelData in WvDutInfo */
WvWord ChannelDataIndex;
/** 0 is capture or DAC, 1 is histogram */
WvWord HistogramEnable;
/** Set histogram max bin value before stop */
WvWord HistogramMaxBin;
/** Data format */
WvDataFormat DataFormat;
/** UNUSED */
WvWord tot_num_acqs;
/** UNUSED */
WvWord num_bufs_used;
/** UNUSED */
WvWord num_acqs_per_buf;
/** UNUSED */
WvWord num_bufs_per_set;
/** UNUSED */
WvWord MultiplexedChannelIndex;
} WvCaptureSetup;